Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping

Kim, Bomsoo; Baek, Chang‐Ki; Кwon, Wook Hyun; Lee, Jawoong; Jeong, Yoon‐Ha; Kim, Dae M.

doi:10.1143/jjap.43.l1581

Cited by 3 publications

(3 citation statements)

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“…[14][15][16][17][18][19] Silicon-oxide-nitride-oxide-silicon (SONOS)-type flash memory cells have a simple structure and appear to be more suitable for miniaturized technology nodes than the conventional floating gate flash memory cells. [20][21][22][23] SONOS memory is a charge trap device in which a multilayer oxide/ nitride/oxide (ONO) stack acts as the gate dielectric. We prepared various silicon nitride (SiN) films by microwave plasma-enhanced chemical vapor deposition (CVD) as charge storage layers in high-performance SONOS memory devices.…”

Section: Introductionmentioning

confidence: 99%

Study of Charge Trap Sites in SiN Films by Hard X-ray Photoelectron Spectroscopy

Kosemura

Takei

Nagata

et al. 2010

Jpn. J. Appl. Phys.

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Estimation of unknown autocomelation coefficients. P. P. Stone (Department of Mechanical Engineering, University of Surrey, Guildford GU2 SXH, England. Physica Scripta (Sweden) 19, 402-410,1919. Certain methods for obtaining autocorrelation coefficients lead to a part knowledge of the total function. The problem discussed in this paper considers the situation where the zero lag coefficient is known, then there are a number of unknown coefficients, followed by knowledge of the remaining part of the function. This particular problem is sometimes encountered when data is randomly or sequentially sampled and there exists a restriction on the sample time.It is intended to propose a method for estimating these unknown lag values based on the properties of the autocorrelation matrix.

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Section: Introductionmentioning

confidence: 99%

Study of Charge Trap Sites in SiN Films by Hard X-ray Photoelectron Spectroscopy

Kosemura

Takei

Nagata

et al. 2010

Jpn. J. Appl. Phys.

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“…Unlike the floating gate device, the polysilicon-oxide-nitride-oxide-silicon (SONOS) and nanocrystal (NC) devices do not have the capacitance coupling interference issue owing to the discrete charge storage concept. 4,5) High-k materials such as HfO 2 and HfGdO have been studied to be the charge trapping layer and are called MOHOS (metal-oxide-high-k trapping layer-oxide-silicon). [6][7][8] The high trap density (10 18 cm À3 ) for both bulk and interface traps, and scaled effective oxide thickness (EOT) of the HfO 2 trapping layer simultaneously lead to the fast operation speed and good data retention of MOHOS Flash memory.…”

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confidence: 99%

Dynamic Charge Centroid on Data Retention of Double-Nanostructure Nonvolatile Memory

Wang¹,

Lin²,

Chen³

et al. 2012

Appl. Phys. Express

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Dynamic charge centroid on retention characteristics of nonvolatile memories with double nanostructures (DNSs), gadolinium oxide nanocrystal (Gd2O3-NC), and hafnium oxide charge-trapping layer (HfO2-CTL) was investigated. Compared with the conventional Gd2O3-NC memory, the DNS memories exhibited superior data retention. In addition, the DNS memory with thicker HfO2-CTL presented more charge loss because the trapped charge centroid was located close to the HfO2/tunneling layer interface. The tendency of charge loss was consistent with the dynamic charge centroid at the low-flat-band-voltage shift region, indicating that the charge centroid location was important for the data retention of DNS nonvolatile memories.

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“…Since the source current decays in time due to soft programming, each data point was obtained dynamically from the peak oscilloscope trace (see inset). 7) When V CG and V D are fixed at 2, 5 V respectively in the fixed gate scheme, I S ranges from 0.23 to 0 mA with erased V T varying from À2 to 2 V. On the other hand, when V CG is varied in such a way that V CG À V T is kept constant, the resulting I S is pinned at a constant level, determined solely by V CG À V T , regardless of the value of V T . This is a key feature of the floating gate device and is extensively used in the present design consideration.…”

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confidence: 99%

Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells

Baek¹,

Kim

Quan

et al. 2005

Jpn. J. Appl. Phys.

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We present an efficient design technique for implementing the optimal ramped gate soft-programming for curing the over-erased flash EEPROM cells. The technique does not rely on any I–V model but is solely based upon using the actual cell performance data and enables accurate prediction of programming time, given supply current (I S). The full utilization of available supply current renders the programming speed much faster and also enables reliable multi-bit soft-programming. The ramped gate scheme induces a strong self-convergence of the simultaneously up-shifted threshold voltages regardless of their initial values or the variations of the shift speed from cell to cell.

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Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping

Cited by 3 publications

References 0 publications

Study of Charge Trap Sites in SiN Films by Hard X-ray Photoelectron Spectroscopy

Study of Charge Trap Sites in SiN Films by Hard X-ray Photoelectron Spectroscopy

Dynamic Charge Centroid on Data Retention of Double-Nanostructure Nonvolatile Memory

Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells

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