The field effect transistor was conceived in 1930s and was demonstrated in 1960s. Since then, MOSFET emerged as the mainstream driver for the digital information technology. Because of the simplicity of structure and low cost of fabrication, it lends to a large scale integration for the multifunctional system-onchip (SOC) applications. Moreover, the device has been relentlessly downsized for higher performance and integration. The physical barriers involved in downscaling the device have prompted the development of process technologies. There has also been the development of device structures from 3D bulk to the gate-all-around nanowire. This chapter is addressed to the discussion of the silicon nanowire field effect transistor (SNWFET). The discussion is carried out in comparison and correlation with the well known theory of MOSFET. The similarities and differences between the two FETs are highlighted, thereby bringing out features unique to SNWFET. Also, an emphasis is placed upon the underlying device physics rather than the device modeling per se. The goal of this chapter is to provide a background by which to comprehend the theories being developed rapidly for SNWFETs.

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Abstract-The erase threshold-voltage (V T)

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