Spatial-filter models to describe IC lithographic behavior

Stirniman, John P.; Rieger, Michael L.

doi:10.1117/12.275978

Cited by 18 publications

(7 citation statements)

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“…We are going to call this point "thepoint of interest" or POT. Despite a very general appearance, this formulation carries some limitations: the etch bias is expressed in an explicit analytical form, in contrast with the surface-slice models [4,5,6,7,8], where bias is calculated indirectly. Formula (1) is the basis for the variable etch bias models, or VEB models.…”

Section: Etch Modeling Methodologymentioning

confidence: 99%

“…These compact models are mainly designed to predict in-resist wafer images, and are not intended to reflect after-resist processing, except for the behavioral [4] and the double-gaussian convolution models [8], both claiming to cover the etch processing effects. These two methods are based on the assumption that the etch effects can be adequately described by the convolution operation.…”

Section: Nondepositivementioning

confidence: 99%

“…Following this analogy we are going to call these simple, OPC-tailored process models, compact process models. Widely used compact models [3,4,5,6,7,8,9] are either derived from the first principles (for example, Brunner-Fergusson resist model [3], or DAIM [7]) or are synthesized to fit experimental data directly (behavioral model [4], or the original Cobb VTR model [6]). …”

Section: Nondepositivementioning

confidence: 99%

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Correction for etch proximity: new models and applications

Granik

2001

SPIE Proceedings

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Short-range etch proximity effects increase intra-die CD variability and degrade the IC performance and yield. Tight control of the etch bias is an increasingly critical factor in realizing the ITRS technology nodes. The 2000 technology nodes revision added a new category, the post-etch "physical" gate length metric, that is 9-17% smaller than "in-resist" gate length. We present new etch proximity correction methods and models designed to reduce negative impact of etch-induced CD variability and increase uniformity of the controlled over-etching. Resolution Enhancement Technologies (RET) design correction methods typically employ "lumped" process models. We found that an alternative methodology based upon separation of the process factors and the related models may yield better accuracy, performance, and better suit the design and process optimization flows. The contributions from the reticle, the optics, the wafer, and etch are individually determined and then used either separately or in aggregation for the most flexible and optimum correction of their respective contributions.The etch corrections are based on the Variable Etch Bias model (VEB model). This semi-empirical model requires experimental CD information to be collected from the test patterns under fixed process conditions (point-process model). It demonstrates excellent fit to the early experimental CD-SEM data gathered to date, which spans a variety of layout features and process conditions. The VEB model works in conjunction with Calibre® software system's Variable Threshold ResistExtended (VTR-E) model, however the etching is modeled separately from the optics and the resist processing. This yields better understanding and more accurate explanation of the experiments than those that are produced by the "lumped" process modeling.The VEB model explains etch-induced bias in terms of the following three proximity characteristics or variables: effective trench width (or pattern separation), pattern density, and effective line width (or pattern granularity). We synthesized and studied their integral representations. Performance fitness of the various weighting, smoothing, and anisotropic integral kernels and their parameters were studied to correctly reflect the etch bias behavior on silicon. We found that depending on the resist composition and layer types (poly or metal), the etch bias can sometimes be explained only by one or two (out of three) proximity variables. The aperture and microloading etch effects are studied and shown to be correctly reflected in the model. We demonstrate how model-based corrections improve CD uniformity of the poly and metal layers by compensating for the iso/dense and inverse-iso/dense biases. More complicated 2-D proximity effects are also captured, which is confirmed by the comparison of the SEM images to the simulations.

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Section: Etch Modeling Methodologymentioning

confidence: 99%

Section: Nondepositivementioning

confidence: 99%

Section: Nondepositivementioning

confidence: 99%

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Correction for etch proximity: new models and applications

Granik

2001

SPIE Proceedings

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“…To achieve appropriate gate CD uniformity, the OPC method has been evolved from the rule-based OPC to the modelbased OPC which has been popularly used under the 130 nm devices. The fast and accurate simulation models describing the optical process enables the automatic correction of the large volume of the full chip layout and shows acceptable accuracy fulfilling the suggested specifications for the 130 nm memory devices [3][4][5]. However, the conventional model-based OPC method has shown its limitation in the application for the etch process proximity correction since the fitting of optical simulation parameters cannot fully explain the loading effect resulting in large bias between the After Development Inspection (ADI) CD and the post etch feature dimension (ACI CD, After Cleaning Inspection CD).…”

Section: Introductionmentioning

confidence: 89%

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

et al. 2004

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Sub-wavelength lithography has made the OPC (Optical Proximity Correction) technology one of the most precious commodities for the fabrication of semiconductor devices. Highly accurate gate CD (Critical Dimension) control and design rule shrinkage have become possible through the development of the OPC technology. Nevertheless, the device specifications require more accurate gate CD control than the current OPC tools can cope with. For the model-based OPC to meet this tight CD specification, the model calibration is very important. Current model-based OPC tools use their OPC models which usually cover the full-chip area with one universal model calibrated by comparing the empirical CD with the simulated CD of specially designed test patterns. Despite its safety, a single model for the fullchip OPC is not accurate for 2-dimensional patterns, and does not take into account the long-range effects of the patterning process such as flare noise or macro loading effect which is closely related to the pattern density.In this work, we suggest a novel idea that applies the dual model to a single OPC process. We have found out that the CD trends of the patterns in the core region and peripheral region of a memory chip differ from each other so that it is difficult to apply the same model for both regions. For the 110 nm DRAM devices with 248nm lithography, we can reduce the gate CD variation up to 40% using the dual model OPC compared with the single model OPC. Since the dual model OPC uses two different models for a correction process, it should be carefully applied not to lose the conformity between the empirical process condition and the physical parameters of the models. The proposed dual model calibrated by the conservative modeling process reduces the gate CD variation by 50% compared with the single model OPC for a 90 nm DRAM device with 193nm lithography.

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“…In order to correct a pattern, the pattern must be broken into correction segments in a process called dissection [1,2]. The pattern is broken into discrete segments to allow localized corrections based on modeled process data.…”

Section: Figure 1: Test Datamentioning

confidence: 99%

Classical control theory applied to OPC correction segment convergence

2004

Self Cite

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Model based Optical Proximity Correction work is currently performed by segmenting patterns in a layout and iteratively applying corrections to these segments for a set number of iterations. This is an open loop control methodology that relies on a finely tuned algorithm to arrive at a proper correction. A goal of this algorithm is to converge in the fewest number of iterations possible. As technology nodes become smaller, different correction areas tend to correct at different rates, and these correction rates are diverging with process node. This leads to more iterations being required to converge to a final OPC solution, the consequence of which is an increased runtime and tapeout cost. The current solution to this problem is to use proportional damping factors to attempt to bring different structure types to a solution. Classical control theory provides tools to optimize the convergence of these processes and to speed up convergence in physical systems. Introducing derivative and integral control while continuing use of proportional control should reduce the number of iterations needed to converge to a final solution as well as optimize the convergence for varied configurations.

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Spatial-filter models to describe IC lithographic behavior

Cited by 18 publications

References 0 publications

Correction for etch proximity: new models and applications

Correction for etch proximity: new models and applications

Accurate gate CD control through the full-chip area using the dual model in the model-based OPC

Classical control theory applied to OPC correction segment convergence

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