Specifications for integrated circuits in telecommunications equipment

Reynolds, F.H.; Lawson, R W; Mellor, P.J.T.

doi:10.1109/proc.1974.9410

Cited by 5 publications

(3 citation statements)

References 12 publications

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“…A complete description of the test results and analysis procedure can be found in the appendices. 12…”

Section: Discussionmentioning

confidence: 99%

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Evaluation of a CMOSSOS process using process validation wafers

Suehle¹,

Linholm²,

Marshall³

1982

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“…A complete description of the test results and analysis procedure can be found in the appendices. 12…”

Section: Discussionmentioning

confidence: 99%

“…It was implemented into a commercial manufacturing facility as a process validation v/afer (PVW) (12,13), a wafer consisting only of identical test patterns. Ninety-five NBS-16 test patterns were fabricated on each 3-in. (76.2-mm) diameter silicon-on-sapphire PVW.…”

Section: An Examplementioning

confidence: 99%

Evaluation of a CMOSSOS process using process validation wafers

Suehle¹,

Linholm²,

Marshall³

1982

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“…A common practice within the semiconductor industry is to arrange probe pads around the periphery of the test pattern and to connect the test structures to the probe pads with metal lines [78]. This is done primarily for convenience in testing; frequently when the test pattern is spotted at selected locations on a wafer of Integrated circuits, the probe pad layout is identical to that of the circuit Itself [79].…”

Section: Test Patterns With Modular Cellsmentioning

confidence: 99%

Semiconductor measurement technology

Bullis¹

1976

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This progress report describes NBS activities directed toward the development of methods of measurement for semiconductor materials, process control, and devices. Both in-house and contract efforts are included. The emphasis is on silicon device technologies. Principal accomplishments during this reporting period included (1) preliminary results of a systematic study of the effects of surface preparation on spreading resistance measurements; (2) development of an optical test for surface quality of sapphire; (3) development of a basis for an exposure sensitivity specification for photoresists; and (4) development of a modular cell concept for test structure design and layout. Also reported are the results of work on four-probe resistivity measurements, comparison of techniques for surface analysis, ion microprobe mass analysis, analysis of process chemicals with flame emission spectrometry, redistribution profiles, thermally stimulated current response of interface states, bias-temperature stress test measurements on MOS capacitors, a high voltage capacitance-voltage method for measuring characteristics of thick insulator films, hydrogen chloride oxidation, ion implantation parameters, methods for determining integrity of passivation overcoats, measurement of free sodium in an oxidation furnace by resonance fluorescence, a square array collector resistor test structure, an electrical alignment test structure, two dimensional wafer maps, test pattern design and analysis for silicon-on-sapphire MOS device technologies^a nondestructive acoustic emission test for beam-lead bonds, wire bond pull test, bondability of doped aluminum metallizations, leakage into double hermetic enclosures, a static expansion dry gas gross leak test, correlation of moisture infusion in semiconductor packages with leak size and device reliability, an automated scanning lowenergy electron probe, an optical flying-spot scanner, scanning electron microscopy, scanning acoustic microscopy, and thermal resistance measurements on power transistors and simple integrated circuits. Supplementary data concerning staff, publications, workshops and symposia, standards committee activities, and technical services are also included as appendices.

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Microelectronic Test Chips for VLSI Electronics

Buehler

1983

Materials and Process Characterization

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Specifications for integrated circuits in telecommunications equipment

Cited by 5 publications

References 12 publications

Evaluation of a CMOSSOS process using process validation wafers

Evaluation of a CMOSSOS process using process validation wafers

Semiconductor measurement technology

Microelectronic Test Chips for VLSI Electronics

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