Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications

Hu, G.; Kim, D.; Kim, J.; Kothandaraman, C.; Lauer, G.; Lee, H K; Marchack, Nathan; Reuter, M. C.; Robertazzi, R. P.; Sun, J. Z.; Suwannasiri, T.; Nowak, Janusz; Trouilloud, P. L.; Woo, S. T.; Worledge, D. C.; Gottwald, Matthias; Brown, S. L.; Doris, B.; D’Emic, C.; Hashemi, Pouya; Houssameddine, D.; He, Qing

doi:10.1109/iedm19573.2019.8993604

Cited by 37 publications

(19 citation statements)

References 1 publication

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“…that when t p =10 ns. This is because the switching variation is smaller at longer pulses, which is consistent with the measurement data of our devices [63] and others' devices [148,204].…”

Section: Transient Simulations: Wer Statisticssupporting

confidence: 93%

“…Due to its intrinsic limitations, the switching speed of STT effect cannot reach sub-ns level, which eliminates the possibility of replacing SRAMs at all cache levels. The fastest stable STT switching that has been demonstrated is 2 ns at a switching current of around 110 µA in 2019 [148]. To further reduce the write power consumption and reach sub-nm speed, novel switching techniques beyond the STT effect such as spin-orbit torque (SOT) effect [34,149,150] and voltage-controlled magnetic anisotropy (VCMA) effect [151,152] are under intensive R&D, which is out of the scope of this thesis.…”

Section: Mtj Evolution Coursementioning

confidence: 99%

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Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…that when t p =10 ns. This is because the switching variation is smaller at longer pulses, which is consistent with the measurement data of our devices [63] and others' devices [148,204].…”

Section: Transient Simulations: Wer Statisticssupporting

confidence: 93%

Section: Mtj Evolution Coursementioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…However, one can observe that the transition area occupies a large area in the contour map, which poses a big design challenge for reliable and deterministic write operations in STT-MRAMs. This clearly indicates that write schemes with a fixed configuration of write voltage and duration are unwise in practice with four drawbacks: 1) large energy consumption, 2) long write latency (performance loss), 3) more susceptible to back-hopping effect [41,42], and 4) reduced endurance or even early breakdown induced by aggressively wearing out the untra-thin MgO tunnel barrier under a large switching current. This has led to the introduction of more flexible write schemes such as write-verify-write scheme by Intel [5] and self-write-termination scheme by TSMC [43].…”

Section: Fault Distribution Vs Write Voltage and Durationmentioning

confidence: 99%

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

Wu¹,

Rao²,

Taouil³

et al. 2021

Preprint

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<div>The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to intermediate (IM) state defects in MTJ devices based on silicon measurements and circuit simulations. An IM state manifests itself as an abnormal third resistive state, which differs from the two bi-stable states of MTJ. We performed silicon measurements on MTJ devices with diameter ranging from 60nm to 120nm; the results show that the occurrence probability of IM state strongly depends on the switching direction, device size, and bias voltage. We demonstrate that the conventional resistor- based fault modeling and test approach fails to appropriately model and test such a defect. Therefore, device-aware test is applied. We first physically model the defect and incorporate it into a Verilog-A MTJ compact model and calibrate it with silicon data. Thereafter, this model is used for a systematic fault analysis based on circuit simulations to obtain accurate and realistic faults in a pre-defined fault space. Our simulation results show that an IM state defect leads to intermittent write transition faults. Finally, we propose and implement a device-aware test solution to detect the IM state defect.</div>

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“…It is promising not only for standalone, but also for embedded memory applications as replacement of conventional volatile CMOS-based and nonvolatile flash memories in systems on chip. STT-MRAM can be integrated in a broad range of applications, from Internet-of-Things to automotive applications [ 3 ] and last level caches [ 8 , 9 , 10 ]. Recently, 1Gb standalone [ 11 ] and embedded STT-MRAM solutions [ 2 , 4 , 12 , 13 ] have been reported and STT-MRAM operation with a timing of a few nanoseconds has been demonstrated [ 8 ].…”

Section: Introductionmentioning

confidence: 99%

Optimization of a Spin-Orbit Torque Switching Scheme Based on Micromagnetic Simulations and Reinforcement Learning

et al. 2021

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Spin-orbit torque memory is a suitable candidate for next generation nonvolatile magnetoresistive random access memory. It combines high-speed operation with excellent endurance, being particularly promising for application in caches. In this work, a two-current pulse magnetic field-free spin-orbit torque switching scheme is combined with reinforcement learning in order to determine current pulse parameters leading to the fastest magnetization switching for the scheme. Based on micromagnetic simulations, it is shown that the switching probability strongly depends on the configuration of the current pulses for cell operation with sub-nanosecond timing. We demonstrate that the implemented reinforcement learning setup is able to determine an optimal pulse configuration to achieve a switching time in the order of 150 ps, which is 50% shorter than the time obtained with non-optimized pulse parameters. Reinforcement learning is a promising tool to automate and further optimize the switching characteristics of the two-pulse scheme. An analysis of the impact of material parameter variations has shown that deterministic switching can be ensured for all cells within the variation space, provided that the current densities of the applied pulses are properly adjusted.

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Spin-transfer torque MRAM with reliable 2 ns writing for last level cache applications

Cited by 37 publications

References 1 publication

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAM

Optimization of a Spin-Orbit Torque Switching Scheme Based on Micromagnetic Simulations and Reinforcement Learning

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