SRAF enhancement using inverse lithography for 32nm hole patterning and beyond

Farys, V.; Chaoui, F.; Entradas, Jorge; Robert, Frédéric; Toublan, Olivier; Trouiller, Yorick

doi:10.1117/12.829894

Cited by 4 publications

(1 citation statement)

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“…It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. Masks computed through the use of ILT are known to provide significantly better lithographic performance than conventional rule-based and even model-based OPC [3][4][5][6] .…”

Section: Introductionmentioning

confidence: 99%

Affordable and process window increasing full chip ILT masks

et al. 2010

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To enable Inverse Lithography Technology (ILT) for production as one of the leading candidates for low-k 1 lithography at 32nm and below, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications [1,2] , it has been shown that the Inverse Synthesizer (IS™) produces ILT full chip mask of contact layer with comparable mask write time with conventional OPC while maintaining the significant litho gains of ILT mask.To fully integrate ILT masks into production for all layers including line and space layers such as poly layer, a number of areas were investigated to further reduce ILT mask complexity and total e-beam shot count. These areas include flexible controls of SRAF placements with respect to local feature sizes, improved Manhattan algorithm, topology based variable Manhattan segmentation, jog alignment and mask data fracture optimization. The impact of these approaches on e-beam shot count and lithography performance of ILT masks is presented in the paper.

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Section: Introductionmentioning

confidence: 99%