Statistical parameter control for optimum design and manufacturability of VLSI circuits

Bolt, M.; Engel, Jan; Klauw, C.L.M. v.d.; Rocchi, Marc

doi:10.1109/ismss.1990.66118

Cited by 9 publications

(6 citation statements)

References 6 publications

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“…Although quality control should be improved as early as possible, first in the design stage, followed by the manufacturing stage, quality control at the end-of-line stage still adds value for the following reasons [1], [2]:…”

Section: Introductionmentioning

confidence: 99%

SHEWMA: an end-of-line SPC scheme using wafer acceptance test data

Fan

Guo

Chang

et al. 2000

IEEE Trans. Semicond. Manufact.

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In this paper, an end-of-line quality control scheme based on wafer acceptance test (WAT) data is presented. Due to the multiple-stream and sequence-disorder effects typically present in the WAT data, an abnormal process shift caused by one machine at an in-line step may become vague for detection using end-of-line WAT data. A methodology for generating robust design parameters for the simultaneous application of Shewhart and EWMA control charts to WAT data is proposed. This SHEWMA scheme is implemented in a foundry environment and its detection and diagnosis-enhancing capabilities are validated using both numerical derivations and fab data. Results show that the SHEWMA scheme is superior to the current practices in detection speed. Its use is complementary to the existing in-line SPC for process integration.

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Section: Introductionmentioning

confidence: 99%

SHEWMA: an end-of-line SPC scheme using wafer acceptance test data

Fan

Guo

Chang

et al. 2000

IEEE Trans. Semicond. Manufact.

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“…This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

“…Secondly, the early statistical device models were verified by matching actual device or circuit performance distributions [5]. This assumes that the production line has attained a state of statistical control.…”

Section: Introductionmentioning

confidence: 99%

“…A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry.…”

mentioning

confidence: 99%

“…The method presented in this work does not rely on process simulation, but uses data collected from transistor characterization, in conjunction with straightforward device physics. Further, the use of manufacturing data ensures that the parameters are measurable using production line capable techniques, and that they explain most of the variation seen on an actual fab line.Secondly, the early statistical device models were verified by matching actual device or circuit performance distributions [5]. This assumes that the production line has attained a state of statistical control.…”

mentioning

confidence: 99%

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A method for modeling the manufacturability of IC designs

Boskin¹,

Spanos²,

Korsh³

ICMTS 93 Proceedings of the 1993 International Conference on Microelectronic Test Structures

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A methodology for modeling the manufacturability of MOS transistors and circuits has been developed. The models are based on a small set of measurable process characterization parameters, whose variation explains the range of performance seen during production. A statistical MOSFET model, based on these measurable process parameters, was developed using global optimization and regression modeling of key fitting parameters to accurately predict transistor characteristics over a wide range of process variation. These same process parameters can be measured on the manufacturing floor, both in-line and at electrical test, and used to predict the performance of the fabricated integrated circuit before packaging and final test. The models for use in manufacturing and design are integrated, and data taken from the manufacturing line can be used to identify process shifts as well as to suggest design improvements for manufacturability enhancement. IntroductionIn today's competitive semiconductor manufacturing environment, it is important to be able to anticipate the effects of processing variation while still designing the product, and to characterize and control this variation while producing it [1,2]. In this work we present a methodology for modeling IC performance in terms of a simple set of process characterization data. First, a MOSFET model is developed, which utilizes a set of process parameters to predict transistor performance across the range of process variation seen on the fabrication line. At the design stage, the MOSFET model can be used for statistical circuit simulation in order to test the manufacturability of the design. These parameters can also be measured during production, and used to predict the performance of fabricated parts, early in the production cycle. A compact, product-specific performance prediction model is built from a combination of simulation results and manufacturing data. The prediction model can be used with production data for process control and production planning.This method has been applied on a commercial 1 Mbit EPROM fabricated in a 1.5 pm CMOS process.This work is based in previous physically based, statistical device modeling efforts [3,4,5]. Despite these previous efforts, however, Design for Manufacturability (DFM) still has limited use in the semiconductor industry. There are several reasons for this problem which are addressed in this research.First, early work in statistical modeling relied heavily on the use of process simulation, with the accompanying prohlem of tuning the simulator to match an actual manufacturing line [6]. The method presented in this work does not rely on process simulation, but uses data collected from transistor characterization, in conjunction with straightforward device physics. Further, the use of manufacturing data ensures that the parameters are measurable using production line capable techniques, and that they explain most of the variation seen on an actual fab line.Secondly, the early statistical device models were verified by matching a...

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