Stenciled conducting bismuth nanowires

Abstract

Stencil lithography is used here for the fabrication of bismuth nanowires using thermal evaporation. This technique provides good electrical contact resistance by having the nanowire structure and the contact pads deposited at the same time. It has also the advantage of modulating nanowires' height as a function of their width. As the evaporated material deposits on the stencil mask, the apertures shrink in size until they are fully clogged and no more material can pass through. Thus, the authors obtain variable-height ͑from 27 to 95 nm͒ nanowires in the same evaporation. Upon their morphological ͑scanning electron microscopy and atomic force microscopy͒ and electrical characterizations, the authors obtain their resistivity, which is independent of the nanowire size and is the lowest reported for physical vapor deposition of Bi nanowires ͑1.2ϫ 10 −3 ⍀ cm͒, only an order of magnitude higher than that of bulk bismuth.

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

“…The fabrication flow is completed by the patterning of Al-gated devices by means of a stencil deposition approach. The full wafer stencil mask contains 100 nm thick SiN membranes with apertures having widths between 100 nm and 1 lm [9]. Through these, material for the transistor gates is deposited.…”

“…Through these, material for the transistor gates is deposited. The stencil is manually aligned to the substrate with 2 lm [9] accuracy using a customized SUSS MA/BA 6 mask aligner [10]. The clamped substrate-stencil setup is placed in an evaporator where 100 nm thick Al gates are deposited.…”

A variable-temperature nanostencil compatible with a low-temperature scanning tunneling microscope/atomic force microscope

“…Atomically clean, high-quality structures with lateral extensions down to a few tens of nanometers [1][2][3] and as thin as a few atomic layers 4 can be fabricated in this way. The stencil technique [5][6][7][8][9][10][11][12][13][14][15] can be applied to a broad range of substrates, [16][17][18][19][20][21] and virtually any vacuum-evaporable material can be deposited. 1-3, 6, 7, 22-24 Limitations of NSL are mainly imposed by geometrical constraints of the shadow mask and the limited lifetime of the mask due to clogging and mechanical stress.…”

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

“…The fabrication flow is completed by the patterning of Al-gated devices by means of a stencil deposition approach. The full wafer stencil mask contains 100-nm-thick SiN membranes with apertures having widths between 100 nm and 1 m [42]. Through these, material for the transistor gates is deposited.…”

“…Through these, material for the transistor gates is deposited. The stencil is manually aligned to the substrate with 2-m [42] accuracy using a customized SUSS MA/BA6 mask aligner [43]. The clamped substrate-stencil setup is placed in an evaporator where 100-nm-thick Al gates are deposited.…”