Strain-induced transconductance enhancement by pattern dependent oxidation in silicon nanowire field-effect transistors

Seike, A.; Tange, Tomoyuki; Sugiura, Yasushi; Tsuchida, I.; Ohta, Hiromichi; Watanabe, Takanobu; Kosemura, Daisuke; Ogura, Atsushi; Ohdomari, Iwao

doi:10.1063/1.2812577

Cited by 41 publications

(40 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, oxidized nanowires should have distributed strains, because the strain depends on the surrounding SiO 2 thickness which changes with position in a nanostructure [4]. Actually, a theoretical analysis indicates a distributed stress in a nanowire [12].…”

Section: Introductionmentioning

confidence: 98%

Analysis of X-ray diffraction curves of trapezoidal Si nanowires with a strain distribution

et al. 2016

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 98%

Analysis of X-ray diffraction curves of trapezoidal Si nanowires with a strain distribution

et al. 2016

View full text Add to dashboard Cite

“…The volume expansion of the oxide during thermal oxidation has long been known to induce strain in silicon, and this has been shown to enhance the transconductance [7] and mobility in silicon nanowires [8], [9]. Normally, one would expect a relaxation of the strain to take place once the straining oxide layer is removed; hence, most studies investigate the strain effects while maintaining the oxide.…”

Section: A Thermal Oxidation As Strain-inducing Techniquementioning

confidence: 99%

“…• C, although such high temperatures are not optimal for strain enhancement as certain viscoelastic relaxation is expected [7]. For future strain enhancement engineering, thermal oxidation should be performed below the glass transition temperature of SiO 2 (960…”

Section: A Thermal Oxidation As Strain-inducing Techniquementioning

confidence: 99%

The High-Mobility Bended n-Channel Silicon Nanowire Transistor

Moselund

Najmzadeh

Dobrosz

et al. 2010

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max ), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

show abstract

“…Quantitative data about carrier mobilities are, however, still missing. Enhancements of the mobility (or transconductance) under strain has been experimentally evidenced in Si NWs with diameters ranging from 150 nm down to quantum-confined < 10 nm NWs [25]- [30]. In this context, quantitative predictions about the transport properties of sub-10-nm Si NWs are highly desirable.…”

Section: Introductionmentioning

confidence: 98%