Stress-induced charge trapping and electrical properties of atomic-layer-deposited HfAlO/Ga₂O₃ metal–oxide–semiconductor capacitors

Abstract

Electrical properties and trapping characteristics of atomic layer deposited Al-rich HfAlO/β-Ga2O3 capacitor were evaluated via constant-voltage stress (CVS), capacitance-voltage (C-V), and current-voltage (I-V) measurements.The magnitude of the stress-induced charge trapping increases with increasing voltage and time. The effective charges (Neff) including the "border" traps located in near-interface oxide, interface traps (Dit) of HfAlO/β-Ga2O3 interface, and fixed charges contribute significantly to the observed charge trapping, and it is found that interface traps contribute more under large stress bias, compared with "border" traps. In addition, the effective charge density is increased with stress time, implying that the contribution of negative effect defect during CVS process could not be negligible.Measurements of high permittivity (10.74), great interface quality (Dit~1×10 12 eV -1 •cm -2 ), and small gate leakage (1.18×10 -5 A/cm 2 at +10 V) has been extracted, suggesting the great electrical properties of Al-rich HfAlO/β-Ga2O3 MOSCAP. According to the above analysis, Al-rich HfAlO is an attractive candidate for normally off Ga2O3 transistors.

Trap Characterization of Atomic-Layer-Deposited Al-Incorporated HfO2 Films on In0.53Ga0.47As

“…Then, the threshold voltage shifts (Δ V TH ) were calculated from the C – V curves of the stressed device and fresh device. A positive shift is observed in all cases, which is indicative of the increased negative charge trapping in the oxide and/or oxide/semiconductor interface . The threshold voltage shift (Δ V TH ) after 2000 s of CVS at 1.5 V for all samples is illustrated in Figure c, where Δ V TH is the difference of the threshold voltage of a fresh device and stressed device.…”

“…A positive shift is observed in all cases, which is indicative of the increased negative charge trapping in the oxide and/or oxide/semiconductor interface. 52 The threshold voltage shift (ΔV TH ) after 2000 s of CVS at 1.5 V for all samples is illustrated in Figure 4c, where ΔV TH is the difference of the threshold voltage of a fresh device and stressed device. The positive shift of the threshold voltage at a positive bias stress indicates electron trapping from the semiconductor to the oxide and passivation of positive charge.…”

Atomic Layer Densification of AlN Passivation Layer on Epitaxial Ge for Enhancement of Reliability and Electrical Performance of High-K Gate Stacks

“…To investigate the reliability of the AlN/HfO 2 gate stacks, we present the CVS measurement in Figure by plotting the variation of the C – V curve with the stress time under a constant positive gate voltage of a stress field ( E stress = 9 MV/cm). A positive shift in the C – V curves was observed in the AlN REF and AlN ALB MOS capacitors, indicating the generation of negative charge traps in the gate dielectric or at the dielectric/semiconductor interface . The flat-band voltage V FB of the C – V curves (Figure ) as a function of the stress time is plotted in Figure .…”

Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions

“…The positive shifts in the threshold voltage in all the deposition cases indicate an increase in the trapping of negative charges in the oxide films. These positive voltage shifts may be attributed to electron trapping in the oxide and/or interface traps at the oxide/semiconductor interface and by assuming the magnitude of the shifts to be linearly proportional to the number of traps present in the films [ 35 ]. Because the lowest number of border traps is observed at the deposition temperature of 300 °C, the smallest voltage shift is also observed at this temperature, as shown in Figure 5 a.…”