Characterization of Electrical Traps Formed in Al2O3 under Various ALD Conditions

Abstract

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al2O3 dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Properties of Al2O3 Thin Films Grown by PE-ALD at Low Temperature Using H2O and O2 Plasma Oxidants

“…The dielectric constant was close to published values for films obtained by ALD and PE-ALD. However, the breakdown electric field was higher than that of ALD layers deposited at low temperatures [17][18][19][20][21] and close to the breakdown field of oxides deposited at temperatures above 200 °C [35,37]. Another advantage of the proposed process is the higher GPC.…”

Nano-Scale Charge Trapping Memory based on Two-Dimensional Conjugated Microporous Polymer

“…Nonetheless, there is a small contribution of Al2O3 to charge trapping in the system. Given the reported interface trap density within ultrathin Al2O3 thin films, which is approximately 10 11 -10 12 cm -2 [27].…”

Multilayer MoS2 Back‐Gate Transistors with ZrO2 Dielectric Layer Optimization for Low‐Power Electronics

“…[29] The C-V hysteresis of the ZrO 2 dielectric grown under 250 and 280 C are lower compared to the samples under other growth temperatures, which means that the interface traps between the Si substrate and the ZrO 2 dielectric are reduced as the growth temperature increases. [30] Figure 3a-e present room-temperature CV multifrequency responses under different ZrO 2 dielectric growth temperatures. The C-V response in the inversion regime is most likely characteristic of the interface state response and may not be the indication of true inversion.…”

“…[ 29 ] The C–V hysteresis of the ZrO 2 dielectric grown under 250 and 280 °C are lower compared to the samples under other growth temperatures, which means that the interface traps between the Si substrate and the ZrO 2 dielectric are reduced as the growth temperature increases. [ 30 ]…”