STT-MRAM with double magnetic tunnel junctions

Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance

“…Perpendicular anisotropy-based magnetic tunnel junctions (p-MTJs) have great potential for reducing power dissipation and scaling to feature sizes below 20 nm, [1][2][3][4][5][6][7] and thus have been extensively studied to develop spin-transfer torque magnetic random access memories (STT-MRAMs) and very-large-scale integrated circuits (VLSIs). [8][9][10][11][12][13] In particular, p-MTJs with a MgO/CoFeB/heavy metal (e.g., Ta, Hf) structure have attracted interest for their enhanced perpendicular anisotropy that originates from both MgO/CoFeB and CoFeB/heavy metal interfaces, [14][15][16][17][18] bringing a reasonable magnetoresistance ratio (TMR) and STT switching critical current density (JC). Furthermore, p-MTJs with a double MgO/CoFeB interface free layer, i.e., MgO/CoFeB/Ta/CoFeB/MgO, have been shown to possess a considerable thermal stability factor (Δ), and JC comparable to that of p-MTJs with a single interface.…”

Perpendicular magnetic tunnel junction (p-MTJ) spin-valves designed with a top Co2Fe6B2 free layer and a nanoscale-thick tungsten bridging and capping layer

“…[35][36][37] However, these structures inherently suffer from a significant number of Ta atoms diffusing into the MgO tunneling barrier at an ex-situ annealing temperature of 400°C. Therefore, the fcc crystallinity of the MgO tunneling barrier degrades abruptly, thereby rapidly decreasing the TMR ratio of the P-MTJ spin-valves.…”

Recent progresses in spin transfer torque-based magnetoresistive random access memory (STT-MRAM)

“…目前已有诸多的STT-MRAM测试芯片和商用产品问 世. 表2 [11,[111][112][113][114][115][116][117][118][119][120][121][122][123][124][125][126][127][128] 列举了近年来学术界和工业界在该领 表 2 近年来的STT-MRAM芯片性能指标 Univ Toronto/Fujitsu Lab [111] 16 Kbit 130 cell: 5.525 R: 9, W: 9-10 a) W: 0.4-0.87 mA 2010 Toshiba [112] 64 Mbit 65 cell: 0.3584, Die: 47.124 30 R: 10 μA, W: 49 μA 2010 Hynix/Grandis [113] 64 Mbit 54 Cell: 0.041 R: <20 W: 140 μA…”

“…Hitachi/Univ Tohoku [114] 32 Mbit 150 cell: 1, chip: 94.83 R: 32, W: 40 W: 300 μA 2010 IBM [115] 4 Kbit array -W: 50 W:~200 μA 2011 Qualcomm [116] 1 Mbit 45 cell: 0.1026, chip: 0.27 R: 10 -2012 Everspin [32,117] 64 Mbit 90 -10~50 -2013 TSMC [118] 1 Mbit 40 macro: 0.56 mm 2 R: 10 W: 281-283 μA 2013 NEC/Univ Tohoku [119] 1 Toshiba [121] 512 Kbit 65 cell: 0.504 8 R: 4 mW, W: 15 mW 2013 Toshiba [122] 1 Mbit 65 cell: 0.45 R: 4, W: 4 R: 0.142 nJ, W: 0.372 nJ 2013 Infineon/TUM [123] 8 Mbit 40 -R: 23 -2014 TDK-Headway [124] 8 Mbit 90 cell: 0.4 W: <5, R: 4 -2015 IBM [125] 4 Kbit array -W: 20-50 -…”