Study of Gate Length Dependence of Two-dimensional Carrier Profile in N-FET by Scanning Tunneling Microscopy

Abstract

We measured the two-dimensional carrier profiles of n-type field effect transistors (n-FETs) with various gate lengths (Lg) by scanning tunneling microscopy. The extension overlap and the distribution of the depletion layers were evaluated to clarify that the measured carrier profiles were consistent with the roll-off characteristic of corresponding transistors. The effect of a pocket implant on a long transistor appeared where the lateral depletion width was locally shorter than the vertical one. In the n-FET with a gate length less than 40 nm, the effect of the pocket impurities from the opposite side mainly appeared as a reduction in the extension overlap in the deep region. Although the presence of this pocket increased the top channel concentration, the short length of the effective channel resulted in the spread of the depletion layer in the deep-channel region via the two-dimensional effect.

Direct Measurement of Offset Spacer Effect on Carrier Profiles in Sub-50 nm p-Metal Oxide Semiconductor Field-Effect Transistors

“…STM is one such technique. [6][7][8][9][10] It has already been reported that STM enables the evaluation of the variation in the 2-D carrier profile in the SDE region of the sub-50 nm p-MOSFETs, which is very consistent with the electrical properties of the corresponding transistors. 5) In this study, the 2-D carrier profiles were measured for the embedded monitors in the same chip after the electrical properties of the p-MOSFETs had been measured.…”

“…The vertical junction was delineated from the current value measured at the metallurgical junction for a reference sample that had been determined by comparison with that measured by secondary ion mass spectroscopy. 5,10) The lateral overlap length is estimated at a depth of 5 nm using the same current value. Figures 6(b) and 6(c) show the 2-D carrier profiles around the SDE and channel regions in sample A and sample B, respectively.…”

Two-dimensional dopant profiling by electrostatic force microscopy using carbon nanotube modified cantilevers

“…Previous studies have paid much attention to analysing the device performance under the assumption of L eff being defined by the LER. However, more recent SCM [15][16][17], SSRM [7,9], and STM [11,12] results all show asymmetric cross-sectional dopant profiles, which indicates that the previous assumption is not correct. In 2004, Xiong and Bokor disclosed their simulation results which showed that the dopant diffusion's root-mean-square (RMS) value was quite different from the LER/LWR ratio, and it was predominantly the dopant profile that contributed to the device performance [28].…”

“…Unfortunately, the back contact fabrication for SSRM is extremely difficult for the plane view sample. The Fujitsu Corporation has succeeded in the plane view detection of a 2D effective channel length under a poly-silicon gate, using ultra-high vacuum scanning tunnelling microscopy (UHV STM) after proper de-layering [10][11][12]. They observed with high resolution the L eff variation induced by the shallow trench isolation (STI) stress, and its dependence on the device pattern.…”

Two-dimensional carrier profiling on operating Si metal-oxide semiconductor field-effect transistor by scanning capacitance microscopy

“…Among them, Kelvin-probe force microscopy ͑KFM͒, 3-5 scanning capacitance microscopy ͑SCM͒, 6-19 scanning capacitance force microscopy ͑SCFM͒, 20-22 scanning spreading resistance microscopy ͑SSRM͒, 23-28 nano-scale potentiometry, 29,30 and scanning tunneling microscopy [31][32][33][34] ͑STM͒ have been used to investigate cross-sectioned semiconductor devices. Among them, Kelvin-probe force microscopy ͑KFM͒, 3-5 scanning capacitance microscopy ͑SCM͒, 6-19 scanning capacitance force microscopy ͑SCFM͒, 20-22 scanning spreading resistance microscopy ͑SSRM͒, 23-28 nano-scale potentiometry, 29,30 and scanning tunneling microscopy [31][32][33][34] ͑STM͒ have been used to investigate cross-sectioned semiconductor devices.…”