Study of surface passivation of strained indium gallium arsenide by vacuum annealing and silane treatment

Abstract

A study of the surface passivation of strained InGaAs using vacuum annealing and silane (SiH4) passivation was reported for the first time. X-ray photoelectron spectroscopy reveals the elimination of As–O bond after vacuum annealing and SiH4 surface passivation. Vacuum annealing eliminated poor quality native oxide on InGaAs surface, while a thin silicon interfacial layer was formed by SiH4 treatment, therefore effectively preventing the InGaAs surface from exposure to an oxidizing ambient during high-k dielectric deposition. Transmission electron micrograph confirmed the existence of a thin oxidized silicon layer between high-k dielectric and InGaAs. By incorporating this surface technology during gate stack formation, TaN/HfAlO/InGaAs metal-oxide-semiconductor capacitors demonstrate superior C-V characteristics with negligible frequency dispersion, small hysteresis, and interface state density as low as (3.5×1011)–(5.0×1011) cm−2 eV−1.

III-V MOSFETs: Surface Passivation, Source/Drain and Channel Strain Engineering, Self-Aligned Contact Metallization

“…The SiH 4 -NH 3 passivation process was developed based on our earlier work on SiH 4 -only passivation (10,20). The native oxides on GaAs and InGaAs substrates were removed [ Fig.…”

Source/Drain Engineering for In0.7Ga0.3As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction

“…Right after this, the samples were quickly loaded into a multiple-chamber MOCVD gate cluster system for interface engineering and HfAlO high-k dielectric deposition. [15][16][17][18][19] Post-gate dielectric deposition anneal (PDA) at 500 C for 60 s was performed prior reactive sputter deposition of TaN. 70 nm of PECVD SiO 2 was also deposited to cover the top surface of TaN gate electrode for selective epitaxy.…”

“…[1][2][3][4][5] Recent research on III-V metaloxide-semiconductor field-effect transistors (MOSFETs) has focused on gate stack and interface engineering, with very promising results obtained. [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] To harness the full potential of III-V MOSFETs, source-drain (S/D) engineering is also an important direction.…”

Ge/Ni–InGaAs Solid-State Reaction for Contact Resistance Reduction on n+ In0.53Ga0.47As

“…Recent research on III-V MOSFETs focuses on indium gallium arsenide (InGaAs) as a channel material and very promising results on gate stack and interface engineering have been obtained. [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] In parallel with research efforts on gate stack technology development, other process modules need to be developed for III-V materials. For example, source/drain (S/D) contact engineering needs to be done to achieve low series resistance (R SD ).…”