Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction

Shih, Chun‐Hsing; Chien, Nguyen Dang

doi:10.1109/led.2011.2164512

Cited by 81 publications

(32 citation statements)

References 14 publications

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“…The source doping profile mainly affects the on-current and SS while the drain doping profile determines the ambipolar behavior [20]. Note that the same parameter may affect the device characteristics differently with different device structures [21,29]. Furthermore, the fabrication process related to required parameters is also a very important issue not only to achieve the desirable device characteristics, but also to reduce the complication in fabrication for enhancing the IC reliability and cost.…”

Section: Design Methodologymentioning

confidence: 99%

“…For long-channel TFETs, the drain doping profile only influences the ambipolar leakages [20]. However, it may exacerbate short-channel effects (SCEs) in sub-10-nm TFETs because of the extreme proximity of the source and drain junctions [21]. Carefully considering the effect of drain, including both its length and doping concentration, is expected to further optimize the device performance.…”

Section: Design Methodologymentioning

confidence: 99%

“…Parameters A and B depend on the carrier effective mass m e , the smaller m e is, the higher is the BTBT current. The effect of small m e in Si 1-x Ge x on the tunneling current is taken into account by modifying parameters A and B to be 2.24×10 21 (eV) 1/2 /cmsV 2 and 15.7×10 6 V/cm(eV) 3/2 , respectively [20]. Eq.…”

Section: Device Structure and Simulation Modelmentioning

confidence: 99%

“…Figure 2(a) plots the current-voltage characteristics of the TFET with graded Si/Ge heterojunction (pure Ge at the source) for illustrating its operation. A very steep SS with relatively high on-current and low off-current is observed, which is attributed to the abrupt transition of tunnel barrier under gate voltage [21]. To visually understand the operation of the device, Fig.…”

Section: Device Structure and Simulation Modelmentioning

confidence: 99%

“…A gate-oxide with high-k dielectrics can significantly boost the on-current, reduce the SS and extend the scalability [15], whereas the double-gate structure doubly improves the on-current [12]. Employing these techniques, a new graded Si/Ge heterojunction TFET has been recently proposed and numerically demonstrated its scalability into sub-10-nm regime with a record average SS of sub-10 mV/decade [21]. In this paper, a proposed extremely short-channel TFET with parameters based on the ITRS specifications of sub-10-nm technologies is meticulously investigated and optimally designed for LSTP applications using the graded Si/Si 1-x Ge x heterojunction.…”

Section: Introductionmentioning

confidence: 99%

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Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

Chien

2018

JST

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This study investigates, by a two-dimensional simulation, the design optimization of a proposed 8 nm tunnel field-effect transistor (TFET) for low standby power (LSTP) applications utilizing graded Si/SiGe heterojunction with device parameters based on the ITRS specifications. The source Ge mole fraction should be designed approximately 0.8 because using lower Ge fractions causes severe short-channel effects while with higher values does not significantly improve the device performance but may create big difficulties in fabrication. Based on simultaneously optimizing the subthreshold swing, on-and off-currents, optimum values of source doping, drain doping and length of the proposed device are approximately 10 20 cm -3 , 10 18 cm -3 , and 10 nm, respectively. The 8 nm graded Si/SiGe TFET with optimized device parameters demonstrates high on-current of 360 µA/µm, low off-current of 0.5 pA/µm, low threshold voltage of 85 mV and very steep subthreshold swing of sub-10 mV/decade. The designed TFET with graded Si/SiGe heterojunction exhibits an excellent performance and makes it an attractive candidate for future LSTP technologies because of its reality to be fabricated with existing FET and SiGe growth techniques.

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Section: Design Methodologymentioning

confidence: 99%

Section: Design Methodologymentioning

confidence: 99%

Section: Device Structure and Simulation Modelmentioning

confidence: 99%

Section: Device Structure and Simulation Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

Chien

2018

JST

Self Cite

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Two‐dimensional Materials for Electronic Applications

Zhang

Wang

2018

Advanced Nanoelectronics

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The successful isolation of graphene in 2004 has attracted great interest to search for potential applications of this unique material and other members of the two-dimensional materials family in electronics, optoelectronics and their interface with the biological systems. At this early stage of 2D materials research, many opportunities and challenges co-exist in this area. This thesis addresses the following issues which are crucial for 2D electronics to be successful, focusing on developing graphene for RF electronics and MoS 2 for digital applications: (1) Development of some of the first graphene-based devices for high frequency applications; (2) Development of compact physical models for graphene transistors; and (3) Understanding the carrier transit

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Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method

Jossy

Vigneswaran

Malarvizhi

et al. 2018

Concurrency and Computation

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Summary Tunnel field effect transistors are used for ultra‐low power application since it is challenging to operate CMOS at very low supply voltage. As tunnel field effect transistor has a very low subthreshold slope due to band to band tunneling (BTBT) mechanism, it has the potential to operate at very low operating voltage. It is necessary that the devices utilized in implantable bio‐medical applications and Internet of Everything (IoE) need to consume very low power. This work presents an analysis of Dual Material Double Gate Tunnel Field effect transistor (DMDG‐TFET). An analytical two dimensional (2D) model has been developed to obtain the analytical expressions for drain current. The 2D Poisson's equation has been used to calculate surface potential in the silicon channel using the superposition approximation, as it considers the short channel effects in the calculation of the current when compared to parabolic approximation. To validate the model, analytical results have been confirmed by comparing with the Sentaurus TCAD simulation results. A reduced subthreshold slope of 31.2 mV/decade is obtained in this paper. It shows that DMDG TFET is a promising candidate for ultra‐low power applications. The subthreshold swing obtained using superposition approximation is more optimized than that of parabolic approximation technique.

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Sub-10-nm Tunnel Field-Effect Transistor With Graded Si/Ge Heterojunction

Cited by 81 publications

References 14 publications

Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

Design Optimization of Extremely Short-Channel Graded Si/Sige Heterojunction Tunnel Field-Effect Transistors for Low Power Applications

Two‐dimensional Materials for Electronic Applications

Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method

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