Sub-20 nm CMOS FinFET technologies

Choi, Yang‐Kyu; Lindert, N.; Xuan, Peiqi; Tang, Stephen; Ha, Daewon; Anderson, Erik H.; King, Tsu‐Jae; Bokor, Jeffrey; Hu, Chenming

doi:10.1109/iedm.2001.979526

Cited by 87 publications

(13 citation statements)

References 9 publications

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“…The iterative progresses of gate length as a function of time line is shown in Fig. 4f 14,[21][22][23][24][25][26][27][28][29][30][31][32][33] . From 2D planar device to 3D FinFET and further GAAFET, the structure of Si transistors gradually changes with better gate control ability.…”

Section: Electrical Measurement and Tcad Simulationmentioning

confidence: 99%

Vertical MoS2 transistors with sub-1-nm gate lengths

Tian

Shen

et al. 2022

Nature

398

230

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Despite 55 years of efforts into short gate length transistors following the Moore's law, the gate length below 1 nm has not been realized. Here, we demonstrated a side-wall monolayer MoS 2 transistors with ultimate 0.34 nm gate length using the edge of graphene as gate electrode. Moreover, large area of chemical vapor deposition graphene and MoS 2 are used for 2-inch wafer production. These ultrashort devices show excellent ON/OFF current ratio of 2 × 10 5 . Simulation results indicate that the MoS 2 sidewall effective channel length approaches 0.34 nm in the ON state. This graphene edge gate combined with MoS 2 vertical channel structure provides an e cient gate control ability and enables the physical gate length scaling down to atomic level, which shows great potential to build next generation electronics.

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Section: Electrical Measurement and Tcad Simulationmentioning

confidence: 99%

Vertical MoS2 transistors with sub-1-nm gate lengths

Tian

Shen

et al. 2022

Nature

398

230

View full text Add to dashboard Cite

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“…It should be noted that such a FinFET is particularly favorable beyond the sub-20 nm CMOS technology node due to the suppression of short-channel effects. Moreover, it has been applied to mass production. , Although the L-FinFET is based on a charge trap memory device composed of gate s ilicon-blocking o xide-charge trap n itride-tunneling o xide-channel s ilicon (SONOS), the tunneling oxide is intentionally removed to shorten the charge retention time because the reservoir operation requires short-term memory capabilities. Due to the absence of the tunneling oxide, charges cannot be stored in the charge trap layer (Si 3 N 4 ) for a long time.…”

Section: Introductionmentioning

confidence: 99%

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Han

Yun

et al. 2023

ACS Appl. Mater. Interfaces

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Reservoir computing can greatly reduce the hardware and training costs of recurrent neural networks with temporal data processing. To implement reservoir computing in a hardware form, physical reservoirs transforming sequential inputs into a high-dimensional feature space are necessary. In this work, a physical reservoir with a leaky fin-shaped field-effect transistor (L-FinFET) is demonstrated by the positive use of a short-term memory property arising from the absence of an energy barrier to suppress the tunneling current. Nevertheless, the L-FinFET reservoir does not lose its multiple memory states. The L-FinFET reservoir consumes very low power when encoding temporal inputs because the gate serves as an enabler of the write operation, even in the off-state, due to its physical insulation from the channel. In addition, the small footprint area arising from the scalability of the FinFET due to its multiple-gate structure is advantageous for reducing the chip size. After the experimental proof of 4-bit reservoir operations with 16 states for temporal signal processing, handwritten digits in the Modified National Institute of Standards and Technology dataset are classified by reservoir computing.

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“…To address this requirement, the development of atomic layer deposition (ALD) process technology has continued. [15][16][17][18] Figures 1(a)-1(b) show the number of (a) ALD and (b) molecular layer deposition (MLD) papers published in the 10 years since 2013. In ALD process research and development, various thin films of nitride, high-k, and metal ALD as well as oxides have been continuously developed, and thin films of excellent quality have been produced.…”

Section: Introductionmentioning

confidence: 99%

Review of molecular layer deposition process and application to area selective deposition via graphitization

Baek

Yang

Park

et al. 2023

Jpn. J. Appl. Phys.

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As patterning technology for manufacturing highly integrated devices develops in the current semiconductor market, sophisticated technology nodes of 5 nm or smaller are required. Area selective deposition (ASD) is a promising technology alternative to traditional top-down methods by reducing-edge placement error (EPE) and creating self-alignment. A new strategy for applying the qualified molecular layer deposition (MLD) process of highly conformal deposition to ASD as an inhibition material is being studied. In the case of metalcones manufactured using an aromatic ring as an organic precursor, graphitic carbonization proceeds through high-temperature annealing, and the inhibition property can be activated by removing surface functional groups. The characteristics of feasible patterning can be noted as metal elements in the thin film are removed during the annealing process, especially in the case of graphitic carbon. In this review, we introduce the potential application of MLD materials in the development of inhibitors for advanced ASD

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Sub-20 nm CMOS FinFET technologies

Cited by 87 publications

References 9 publications

Vertical MoS2 transistors with sub-1-nm gate lengths

Vertical MoS2 transistors with sub-1-nm gate lengths

Leaky FinFET for Reservoir Computing with Temporal Signal Processing

Review of molecular layer deposition process and application to area selective deposition via graphitization

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