Switched current filter design with the use of integrators composed of equal size transistors

Handkiewicz, Andrzej; Rudnicki, R.; Kropidłowski, Marek

doi:10.1109/ecctd.2005.1522921

Cited by 4 publications

(7 citation statements)

References 4 publications

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“…This indicates the limited accuracy of the transistor model with respect to this parasitic effect. In particular the experiments did not confirm the possibility, observed during simulations [13], of tuning the SI filters using the rise/fall time of the clock. In addition, in the simulation the minimum permissible rise/fall time was only 4 ns, while the integrator on the chip operates correctly with a rise/fall time of 2.5 ns, which is attainable in experiments.…”

Section: Resultscontrasting

confidence: 61%

Section: Resultsmentioning

confidence: 97%

“…In addition, in the simulation the minimum permissible rise/fall time was only 4 ns, while the integrator on the chip operates correctly with a rise/fall time of 2.5 ns, which is attainable in experiments. It is shown also in [13] that the power consumption of a third-order elliptic filter …”

Section: Resultsmentioning

confidence: 97%

“…This confirms the satisfactory precision of the operation of the designed integrator. It is shown in [13] that filters realized with the use of the integrator can perform better than filters presented in the literature [10] by one order of magnitude in power consumption and chip area. Concluding the measurement results, we can say that the parameters such as the power consumption, the current mirror scaling factor , the coefficient k of integrators, and the noise level obtained during analysis and simulation are close to that obtained during the measurements.…”

Section: Resultsmentioning

confidence: 99%

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Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Rudnicki¹,

Kropidłowski²,

Handkiewicz³

2008

Circuit Theory & Apps

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SUMMARYThe switched-current (SI) technique permits realizing analog discrete-time circuits in standard digital CMOS technology. A very important property of the analog part of a system on a chip is the possibility it offers for realizing some functions of a digital circuit, but with reduced power consumption. In this paper, a low power SI integrator is presented. It is shown that an integrator consuming a fraction of a milliwatt can be designed in 0.35 m CMOS technology with the use of narrow transistor channels, and with the channel length as a design parameter. The impact of the rise/fall time of the clock signal on the integrator operation is observed. It is shown that this effect can be reduced when the proper switch dimensions are taken for the integrator. Analysis and measurements of the integrator noise are presented. The integrator was built with equal size transistors, yielding less sensitivity to variations in production parameters. An experimental chip in 0.35 m CMOS technology was fabricated, and measurements are compared with results obtained during analysis and simulations. In order to verify the properties of the designed integrator experimentally, a first-order filter is built with the use of elementary cells on the chip.

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Section: Resultscontrasting

confidence: 61%

Section: Resultsmentioning

confidence: 97%

Section: Resultsmentioning

confidence: 97%

Section: Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Rudnicki¹,

Kropidłowski²,

Handkiewicz³

2008

Circuit Theory & Apps

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“…The relative area of the capacitor matrix is reduced in this case to 582.4950. The gyrator-capacitor prototype circuit is also suitable for switched-capacitor (SC) and switchedcurrent (SI) filter implementations [12,25,26]. In these techniques, the basic cells are integrators, and the number required is equal to the filter order.…”

Section: Implementation Of Filter Pairsmentioning

confidence: 99%

Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Handkiewicz

Katarzyński

Szczęsny

et al. 2010

Circuit Theory & Apps

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SUMMARYThe paper presents an algorithmic approach to a low-sensitivity design strategy for analog filter pairs based on a gyrator-capacitor prototype circuit. The general structure of the prototype circuit is proposed. It assumed that the generic structure of the prototype circuit can evolve, with the use of additional gyrators, into a circuit with increased redundancy. It is shown that symbolic analysis of the prototype circuit, used to formulate a set of nonlinear algebraic equations, is necessary to achieve a sufficiently high algorithm operation speed. To find a solution to this specific system of nonlinear algebraic equations, different numerical methods are compared. The modified Hooke and Jeeves algorithm is found to be the most effective. The elaborated algorithms and programs are illustrated with the seventh-order filter pair example. The obtained filter is better than the filter obtained using LC ladder structures with respect to chip area and power consumption, and these improvements are obtained without loss of sensitivity properties.

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Automated Design and Layout Generation for Switched Current Circuits

Śniatała

Rudnicki

2006 IEEE International Symposium on Circuits and Systems

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Switched current filter design with the use of integrators composed of equal size transistors

Cited by 4 publications

References 4 publications

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Analog filter pair design on the basis of a gyrator–capacitor prototype circuit

Automated Design and Layout Generation for Switched Current Circuits

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