Switched-current memory circuits for high-precision applications

Guggenbühl, W.; Di, Jiandong; Goette, Josef

doi:10.1109/4.309907

Cited by 38 publications

(11 citation statements)

References 22 publications

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“…During , is evaluated with bandwidth by the following stage, then (11) where is the in-band noise current of M1. Therefore, the power of the overall output noise current is (12) Similar results have been derived by Nairn and Biman [38].…”

Section: Analytical Mdac Modelsmentioning

confidence: 99%

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-m CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution ( 12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.Index Terms-Analog computer-aided analysis and design (CAD), distortion, equation based, multiplying digital-to-analog converter (MDAC), noise, pipeline analog-to-digital converters (ADCs), simulation based, switched capacitor, switched current.

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Section: Analytical Mdac Modelsmentioning

confidence: 99%

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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“…Many methods have been proposed to reduce the error effects in SI circuits [12], and circuits with 11-bit equivalent accuracy have been reported [15]. However, the more sophisticated methods of error compensation in SI cells require more complex circuitry, and therefore, the design of an AP will involve tradeoffs between accuracy, speed, area and power.…”

Section: Signal-dependent Error Cancellationmentioning

confidence: 99%

A CMOS general-purpose sampled-data analog processing element

Dudek

Hicks

2000

IEEE Trans. Circuits Syst. II

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“…The SI integrator circuit shown in Fig. 4 is taken for the experiment and its ideal transfer function can be expressed as follows: (10) Applying the simple CSH model, the SI integrators, including first generation, second generation, dynamic, cascode, folded cascode structure, and others [18], [19], [20], all can be simplified as the model shown in Fig. 5 where the nonideal effects have been taken into account.…”

Section: Efficient System Analysis Basedmentioning

confidence: 99%

“…Moreover, the number of the transistors used in these circuits is doubled. By using Miller capacitors [10], [11], the modified SI circuits can eliminate considerable feedthrough errors. However, their speed is substantially reduced and the most attractive advantage of SI circuits, i.e., no need of linear capacitors, is lost.…”

mentioning

confidence: 99%

Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

Kuo

Lee

Chen

1997

IEEE Trans. Circuits Syst. II

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This paper presents a new offset current cancellation technique called multiple-path feedback compensation (MPFC) for greatly reducing offset currents at both output and internal nodes of SI circuits and systems. In order to analyze the effects and the statistical distribution of dc current offsets of large SI systems, a very simple and efficient SI model is first used. This model can be used for fast, accurate, statistical, and systematic analyzes of system characteristics such as offset current, frequency response, stability, scaling, and sensitivity. Based on the model, a complex SI system can be transferred to a simple signal flow graph, which can be represented by linear state equations. From the state equations, statistical Monte Carlo simulation is used to obtain optimal MPFC coefficients. A fifth-order Chebyshev SI filter is illustrated as an example for implementation and verification of the proposed MPFC technique. Ninety test chips have been fabricated with a 1-m CMOS n-well digital process.Increased percentages of circuit area and power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signalto-noise ratio (PSNR) is increased by 3 dB and the total harmonic distortion is reduced by 10 dB.

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Switched-current memory circuits for high-precision applications

Cited by 38 publications

References 22 publications

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

A CMOS general-purpose sampled-data analog processing element

Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

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