Switched-current signal processing for video frequencies and beyond

Switched-current delta-sigma A/D converters

“…Being able to obtain all the advantage of fully differential structures, fully differential SI circuits have an added advantage, i.e., reduced CFT error [2,26]. In Fig.…”

“…The main difference between the memory cells of Fig. 11 and the one proposed in [26] is the use of the level shifter in Fig. 11, consisting of a level shifting transistor TL and its biasing transistors TLN and TLe.…”

“…is the gate-source voltage of TL at the quiescent condition). The drain potential of the memory cell of T2j is thus set by its saturation requirement not by the need to turn on the transistors TN as in [26]. Therefore low-voltage operation is now possible [12,16].…”

“…The memory transistor pair consist of transistors MN and Me, and the GGA consists of the grounded-gate transistor TG, current biasing transistor Te and cascoded current bias transistors Tc and TN. The class AB memory cell bears some resemblance to the class A memory cells in [12,16,26], where the p-type memory transistor was used as a current biasing transistor. The class AB configuration as shown in Fig.…”

A high-performance SI memory cell

“…The accuracy is similar to the cell presented in [7] which has a conversion rate of 1 ms. In [8] the clock rate is about 100 ns but the precision is less. In [9] an S21 cell is proposed with a simulated error of 700 ppm at 15 ns (designed in 0.8 pm CMOS).…”