Switching activity analysis for sequential circuits using Boolean approximation method

Uchino, T.; Minami, F.; Murakata, M.; Mitsuhashi, T.

doi:10.1109/lpe.1996.542734

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…Actually, the skew value is less than 0.2ns and it is comparable to that of non gated-clock circuit. Power dissipation of the gated-clock circuit and the non gated-clock circuit is analyzed by ProPower [9,10]. ProPower is a power estimator employing probabilistic approach to calculate signal probabilities and switching activities.…”

Section: Resultsmentioning

confidence: 99%

A clock-gating method for low-power LSI design

Kitahara

Minami

Ueda

et al.

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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-This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed GatedClock Tree Synthesizer for the first issue, and Timing Constraints Generator and Clock Delay Estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2ns keeping timing constraints for enable-logic parts.

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Section: Resultsmentioning

confidence: 99%

A clock-gating method for low-power LSI design

Kitahara

Minami

Ueda

et al.

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Self Cite

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A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Gangadhar

Tragoudas

2013

J Electron Test

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Probabilistic analysis of safety-critical adaptive systems with temporal dependences

Adler

Domis

Furster

et al. 2008

2008 Annual Reliability and Maintainability Symposium

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Dynamic adaptation means that components are reconfigured at run time. Consequently, the degree to which a system fulfils its functional and safety requirements depends on the current system configuration at run time. The probability of a violation of functional requirements in combination with an importance factor for each requirement gives us a measure for reliability. In the same way, the degree of violation of safety requirements can be a measure for safety. These measures can easily be derived based on the probabilities of possible system configurations. For this purpose, we are introducing a new probabilistic analysis technique that determines configuration probabilities based on Fault trees, Binary Decision Diagrams (BDDs) and Markov chains. Through our recent work we have been able to determine configuration probabilities of systems but we neglected timing aspects [1]. Timing delays have impact on the adaptation behavior and are necessary to handle cyclic dependences. The contribution of the present article is to extend analysis towards models with timing delays. This technique builds upon the Methodologies and Architectures for Runtime Adaptive Systems (MARS) [2], a modeling concept we use for specifying the adaptation behavior of a system at design time. The results of this paper determine configuration probabilities, that are necessary to quantify the fulfillment of functional and safety requirements by adaptive systems

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Switching activity analysis for sequential circuits using Boolean approximation method

Cited by 4 publications

References 7 publications

A clock-gating method for low-power LSI design

A clock-gating method for low-power LSI design

A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Probabilistic analysis of safety-critical adaptive systems with temporal dependences

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