Synaptic behaviors of a single metal–oxide–metal resistive device

Choi, Sang Jun; Kim, Guk Bae; Lee, Kyoobin; Kim, Ki Hong; Yang, Wonyoung; Cho, Soo-Haeng; Bae, Hyung Jin; Seo, Dong Seok; Kim, Sang Il; Lee, Kyung Jin

doi:10.1007/s00339-011-6282-7

Cited by 46 publications

(25 citation statements)

References 27 publications

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“…Compared with other emerging electronic synapses561113141627, the analog chalcogenide synapse displayed the advantages of ultralow operation voltage, ultrafast synaptic events and feasibility of time window tuning (Fig. 4d).…”

Section: Discussionmentioning

confidence: 99%

“…In recent years, researchers have demonstrated the feasibility of various nanoscale electronic devices that emulate representative neuronal and synaptic functions, such as synaptic modifications, excitatory/inhibitory postsynaptic currents and memory consolidation345678910111213141516. The resistance or conductance of the electronic synapses in these physical implementations represents the synaptic efficacy (synaptic weight), which is the connection strength between neurons17.…”

mentioning

confidence: 99%

“…The resistance or conductance of the electronic synapses in these physical implementations represents the synaptic efficacy (synaptic weight), which is the connection strength between neurons17. The Hebbian spike-timing-dependent plasticity (STDP) rule has been a commonly demonstrated biological function in various electronic synapses345613141516. This function has been experimentally observed in a wide variety of neural circuits in different species, ranging from locusts to humans, and is regarded as the basis for learning and memory181920.…”

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confidence: 99%

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Ultrafast Synaptic Events in a Chalcogenide Memristor

Zhong

et al. 2013

Sci Rep

363

240

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Compact and power-efficient plastic electronic synapses are of fundamental importance to overcoming the bottlenecks of developing a neuromorphic chip. Memristor is a strong contender among the various electronic synapses in existence today. However, the speeds of synaptic events are relatively slow in most attempts at emulating synapses due to the material-related mechanism. Here we revealed the intrinsic memristance of stoichiometric crystalline Ge2Sb2Te5 that originates from the charge trapping and releasing by the defects. The device resistance states, representing synaptic weights, were precisely modulated by 30 ns potentiating/depressing electrical pulses. We demonstrated four spike-timing-dependent plasticity (STDP) forms by applying programmed pre- and postsynaptic spiking pulse pairs in different time windows ranging from 50 ms down to 500 ns, the latter of which is 105 times faster than the speed of STDP in human brain. This study provides new opportunities for building ultrafast neuromorphic computing systems and surpassing Von Neumann architecture.

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Section: Discussionmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Ultrafast Synaptic Events in a Chalcogenide Memristor

Zhong

et al. 2013

Sci Rep

363

240

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“…As mentioned already, the simulation results were based on I -V sweeping measurements in which each voltage was applied for 80 μs; contrastingly, the duration of the voltage pulses was 1 μs in the experiments. Even for low applied voltages, when the duration of the applied voltage is relatively long, the high diffusivity of copper ions in the Cu 1.5 O layer induces electrical diffusion [14]. Nevertheless, these observations suggest that the non-linearity fitting parameter α still allows efficient quantitative evaluation of a device's capability for multibit operation.…”

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confidence: 96%

Modeling of a Parameter to Evaluate Multilevel Operation of Bipolar Oxide Resistive Device

Choi

Kim

Yang

et al. 2014

IEEE Trans. Electron Devices

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We propose a simple and efficient model using a phenomenological fitting parameter for current-voltage sweeps to describe vacancy dynamics in oxide resistive devices, and thereby to explain the relation between physical state and resistance in these devices. The fitting parameter serves as a figure of merit, describing a device's capability for multibit operation. The understanding achieved through this model allows efficient evaluation of device performance factors including the maximum ON/ OFF ratio and the multiresistance property. Index Terms-Copper oxide, multibit operation, vacancy.O XIDE resistive devices are well known to have the advantages of a simple structure and superior performance, and their multiple resistance properties have drawn attention to their application in future memory systems. In such applications, the ability to operate at multiple resistance levels is a key criterion representing a device's performance [1]- [5].Accordingly, physical models have been proposed to explain the multiple resistance states in bipolar oxide resistive devices during electrical operation. Most previous studies in this area [6]- [11] have concentrated on the change in the physical state during the switching processes. Among them, Yu, et al. [6] described the change in resistance according to the duration of applied voltage and Degraeve, et al. [7] explained the change in resistance using a new model they called the hour glass model. However, there is a need for a more simplified and practical model to describe the physical phenomena during electrical operation using a simple phenomenological parameter; this would allow evaluation of the performance of oxide resistive devices in terms of their multibit storage ability. Therefore, our objective in this brief is to suggest a new model that will use a simple phenomenological parameter to provide a more practical description of physical phenomena during resistance changes.For these purposes, we propose a new model based on experimental results [12] that demonstrate that the change in resistance of an oxide device is determined by the changes in current paths at the interface between the electrode and Manuscript

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“…14). Subsequently, many studies demonstrated that a memristor can be used as an electronic synapse with its conductance representing the synaptic weight [15][16][17][18][19][20][21][22][23][24][25] . Although synaptic operation of memristors has been widely demonstrated, implementation of even a simple ANN is challenging.…”

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confidence: 99%

Associative memory realized by a reconfigurable memristive Hopfield neural network

et al. 2015

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Although synaptic behaviours of memristors have been widely demonstrated, implementation of an even simple artificial neural network is still a great challenge. In this work, we demonstrate the associative memory on the basis of a memristive Hopfield network. Different patterns can be stored into the memristive Hopfield network by tuning the resistance of the memristors, and the pre-stored patterns can be successfully retrieved directly or through some associative intermediate states, being analogous to the associative memory behaviour. Both single-associative memory and multi-associative memories can be realized with the memristive Hopfield network.

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Synaptic behaviors of a single metal–oxide–metal resistive device

Cited by 46 publications

References 27 publications

Ultrafast Synaptic Events in a Chalcogenide Memristor

Ultrafast Synaptic Events in a Chalcogenide Memristor

Modeling of a Parameter to Evaluate Multilevel Operation of Bipolar Oxide Resistive Device

Associative memory realized by a reconfigurable memristive Hopfield neural network

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