2019 IEEE 69th Electronic Components and Technology Conference (ECTC) 2019
DOI: 10.1109/ectc.2019.00189
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System Co-design of a 600V GaN FET Power Stage with Integrated Driver in a QFN System-in-Package (QFN-SiP)

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Cited by 3 publications
(1 citation statement)
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“…Despite reduced parasitic inductance, the drivers used were all packaged chips. To further reduce the inductance between the driver chip output terminal and the GaN HEMT gate, as well as the inductance in driver grounding, drivers and GaN HEMT dies were integrated into an 8.00 × 8.00 mm quad flat no-leads (QFN) package by Texas Instruments Incorporated [14]. On the other hand, it was shown that flip-chip technology can further reduce the parasitic inductance and make modules more compact than general wire bonding [15,16].…”
Section: Introductionmentioning
confidence: 99%
“…Despite reduced parasitic inductance, the drivers used were all packaged chips. To further reduce the inductance between the driver chip output terminal and the GaN HEMT gate, as well as the inductance in driver grounding, drivers and GaN HEMT dies were integrated into an 8.00 × 8.00 mm quad flat no-leads (QFN) package by Texas Instruments Incorporated [14]. On the other hand, it was shown that flip-chip technology can further reduce the parasitic inductance and make modules more compact than general wire bonding [15,16].…”
Section: Introductionmentioning
confidence: 99%