System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV

Kumagai, K.; Yang, Changqi; Izumino, H.; Narita, Nagato; Shinjo, K.; Iwashita, S.; Nakaoka, Y.; Kawamura, T.; Komabashiri, H.; Minato, T.; Arnbo, A.; Suzuki, Teruhiko; Liu, Zhenyu; Song, Yang; Goto, Satoshi; Ikenaga, Takeshi; Mabuchi, Yusaku; Yoshida, Kenji

doi:10.1109/isscc.2006.1696226

Cited by 41 publications

(22 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…• Micro-bump [4,12] is a die-to-die interconnection through solder balls. This approach is limited to the face-to-face connection of only two dies.…”

Section: Wired 3-d Interconnectionmentioning

confidence: 99%

See 1 more Smart Citation

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani

Take

Sasaki

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology that can connect more than two known-good-dies without wire connections. Each chip has data transceivers for uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a single vertical ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring network, we use the bubble flow control which is more flexible and efficient compared to the conventional VC-based deadlock avoidance. We implemented a real 3-D chip that has onchip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. The vertical bubble flow control is compared with the conventional VC-based approach and vertical bus in terms of the throughput, hardware amount, and application performance using a full system CMP simulator. The results show that the proposed vertical bubble flow network outperforms the VC-based approach by 7.9%-12.5% with a 33.5% smaller router area. *

show abstract

“…• Micro-bump [4,12] is a die-to-die interconnection through solder balls. This approach is limited to the face-to-face connection of only two dies.…”

Section: Wired 3-d Interconnectionmentioning

confidence: 99%

“…Various interconnection technologies have been developed to be used as a medium for the 3-D NoCs: wire-bonding, micro-bump [4,12], wireless (e.g., capacitive or inductive coupling) [7,9,19,20] between stacked dies, and throughsilicon via (TSV) [5,7] between stacked wafers. The comparisons of these 3-D IC technologies are discussed in [7].…”

Section: Introductionmentioning

confidence: 99%

A vertical bubble flow network using inductive-coupling for 3-D CMPs

Matsutani

Take

Sasaki

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

View full text Add to dashboard Cite

show abstract

“…Therefore, in scenario 3, we replace the IO transceivers with CMOS based buffers. Finally, in scenario 4, we take advantage of the interconnect density of the TSVs, increasing the amount of I/O pins between DRAM and logic die (similar to [10]). …”

Section: Scenarios For 3d Stacked Drammentioning

confidence: 99%

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Facchini

Carlson

Vignon

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

Abstract-Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottleneck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-theart industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.

show abstract

“…Wired interconnections (e.g. wire bonding, micro-bump bonding [1], and through-silicon-via (TSV) [2]) have been mature techniques. Especially, TSV is advantageous in terms of high bandwidth and small footprint, and has been utilized in memory systems including HMC and HMB.…”

Section: Introductionmentioning

confidence: 99%

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Nomura

Matsushita

Kadomoto

et al. 2018

IJNC

View full text Add to dashboard Cite

A wireless inductive coupling ThruChip Interface (TCI) is a flexible system-in-package (SiP) technique which enables to build a powerful interconnection network between stacked chips. For easy use of TCI, we have developed intellectual properties (IPs), and proposed an interconnection network which can make the use of IPs. We also developed a real chip embedded the IP, and evaluated the performance. By stacking multiple chips with the proposed IP, an inter-chip network with link-to-link flow control by piggyback control is established. The new proposed escalator network which uses piggyback of the credit packets outperforms the ring network used in the first prototype by 28%-59% in terms of throughput. The performance overhead by the piggyback control was less than 3%-4% of that without control messages.

show abstract

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV

Cited by 41 publications

References 1 publication

A vertical bubble flow network using inductive-coupling for 3-D CMPs

A vertical bubble flow network using inductive-coupling for 3-D CMPs

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface

Contact Info

Product

Resources

About