System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management

Bouhadiba, Tayeb; Moy, Matthieu; Maraninchi, Florence

doi:10.7873/date.2013.327

Cited by 20 publications

(3 citation statements)

References 11 publications

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“…Recently, Bouhadiba et al [5] proposed a system-level sim ulation method including functionality and power consumption estimation for softcore based FPGA circuit but their approach suffers in terms of speed as they use Cycle-Accurate (CA) simulation. To overcome this drawback the Functional Level Power Analysis (FLPA) was proposed [12], which relies on the identification of a set of functional blocks that influence the power consumption of the target component.…”

Section: S �mentioning

confidence: 99%

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri

Palomar

Moreno

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development.The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed.The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE.The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.

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Section: S �mentioning

confidence: 99%

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri

Palomar

Moreno

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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“…Bouhadiba et al [26] proposed a study on energy consumption at TLM level based on a real FPGA system, designed with Xilinx EDK. Studies such as M.Baharloo et al [24] propose models to make the estimation power of systems on chip, the first in an RTL level with a NOC (R. Garibotti et al 2015) network and the second with a bus network at TLM level L. Caiet al [27].…”

Section: Energy Consumptionmentioning

confidence: 99%

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

et al. 2021

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Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

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“…At transaction-level, research investigations are mainly on power characterization [3,4,5]. The main focus is on early power analysis and estimation.…”

Section: Introductionmentioning

confidence: 99%

Architectural low-power design using transaction-based system modeling and simulation

Mischkalla

Mueller

2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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Energy efficiency drives the development of more and more complex low-power designs. Based on dynamic power management techniques, multiple voltage islands as well as a huge amount of power states are specified that have to be tested carefully. In this context, low-power design should start at an early stage using state-of-the-art system-level modeling and simulation techniques. However, there is neither a programming language nor any modeling standard that reflects variable power together with its functional side effects in a well-suited abstract manner. To overcome this limitation, we present a modeling approach on top of SystemC TLM to capture low-power design characteristics at electronic system-level. We demonstrate the usability by means of an existing open-source low-power design. The experimental results show that appropriate TLM instrumentation cause only minimal simulation overhead, but offer sufficient details to identify common low-power design errors.

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System-Level Modeling of Energy in TLM for Early Validation of Power and Thermal Management

Cited by 20 publications

References 11 publications

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)

Architectural low-power design using transaction-based system modeling and simulation

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