Tail-Biting Globally-Coupled LDPC Codes

Zhang, Ji; Bai, Baoming; Li, Shuangyang; Zhu, Min; Li, Huaan

doi:10.1109/tcomm.2019.2944621

Cited by 11 publications

(3 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…GC-LDPC codes are a class of quasi-cyclic LDPC (QC-LDPC) codes that have been studied intensively at present [16,17,18,19]. GC-LDPC codes are essentially a class of two-dimensional QC-LDPC codes.…”

Section: Kb Gc-ldpc Codes Designed For Flash Memoriesmentioning

confidence: 99%

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Bao,

Guan,

Liang

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

Globally-coupled low-density parity check (GC-LDPC) codes have shown great application potential in the error correction of NAND Flash memories. However, the existing LDPC encoder architectures cannot fully use the structure characteristic of GC-LDPC codes. In this letter, focusing on the particular globally-coupled structure, we propose a memory-efficient multiplex-parallel GC-LDPC encoding method and corresponding efficient GC-LDPC encoder architecture. By reusing the local submatrices and optimizing the operation order of piecewise parity bits, the proposed encoding method has low storage overhead and encoding complexity. Then, based on the designed extended shift-register-adderaccumulator (E-SRAA) unit and barrel shifter, we optimize the operator scheduling of the proposed GC-LDPC encoding method when its local encoding is different. The implementation results under various FPGA technologies show that the proposed GC-LDPC encoder architecture achieves a markedly higher throughput-to-resource overhead ratio than existing similar LDPC encoder architectures. Meanwhile, it can meet the bandwidth requirement of ONFI 6.0.

show abstract

Section: Kb Gc-ldpc Codes Designed For Flash Memoriesmentioning

confidence: 99%

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Bao,

Guan,

Liang

et al. 2024

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…A proper designed codebook can eliminate the error patterns with relatively small Euclidean distances and overcome the influence of erasure and noise. 2) Enhanced communication efficiency: Channel coding can help the convergence speed of the graph [119]. In particular, the code can be designed to maximize the mutual information between the broadcasted message and the the extrinsic information from each vehicle in a statistical way according to the channel model.…”

Section: B Case Ii: Network Decodingmentioning

confidence: 99%

Distributed Estimation Framework for Beyond 5G Intelligent Vehicular Networks

Yuan

Xiang

et al. 2020

IEEE Open J. Veh. Technol.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Different from the traditional channel encoding algorithms, the key idea of spinal codes is that a similar structure of convolutional code [2,3] and an irreversible hash function to generate pseudorandom sequences are adopted. Compared with the fixedrate codes such as turbo codes [4,5] and low-density parity check (LDPC) codes [6,7], rateless codes can adapt to the dynamic channel and generate infinite modulation symbols to send continuously without feedback [6]. As shown in [8,9], spinal codes have been proved that they can achieve the capacities of both additive white Gaussian noise (AWGN) channel and the binary symmetric channel (BSC) with short message length and pseudorandom like codewords.…”

Section: Introductionmentioning

confidence: 99%

Improved encoding structure and decoding algorithms for spinal codes

Huang

Wang

2022

J. of Syst. Eng. Electron.

View full text Add to dashboard Cite

To improve the error correction performance, an innovative encoding structure with tail-biting for spinal codes is designed. Furthermore, an adaptive forward stack decoding (A-FSD) algorithm with lower complexity for spinal codes is proposed. In the A-FSD algorithm, a flexible threshold parameter is set by a variable channel state to narrow the scale of nodes accessed. On this basis, a new decoding method of AFSD with early termination (AFSD-ET) is further proposed. The AFSD-ET decoder not only has the ability of dynamically modifying the number of stored nodes, but also adopts the early termination criterion to curtail complexity. The complexity and related parameters are verified through a series of simulations. The simulation results show that the proposed spinal codes with tail-biting and the AFSD-ET decoding algorithms can reduce the complexity and improve the decoding rate without sacrificing correct decoding performance.

show abstract

Tail-Biting Globally-Coupled LDPC Codes

Cited by 11 publications

References 28 publications

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

Distributed Estimation Framework for Beyond 5G Intelligent Vehicular Networks

Improved encoding structure and decoding algorithms for spinal codes

Contact Info

Product

Resources

About