Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment

Loo, Sin Ming; Wells, B. Earl

doi:10.1287/ijoc.1040.0106

Cited by 22 publications

(4 citation statements)

References 27 publications

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“…A static scheduler needs all tasks timing information in advance and it uses intensive complex algorithms to achieve optimal results. In [1] a high-level model called reconfigurable system design model (RSDM) is introduced.…”

Section: Related Workmentioning

confidence: 99%

Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems

Al-Wattar

Areibi

Saffih

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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Modern reconfigurable devices such as FPGAs can be reconfigured at run time. Some of them can be dynamically partially reconfigured, which means part of the FPGA is changed without interrupting other parts. This feature adds tremendous flexibility to the Reconfigurable Computing (RC) Field but also introduces challenges. Reconfigurable Operating Systems tend to ease applications development and most importantly applications verifications and maintenance. In this paper we propose novel scheduling algorithms for reconfigurable computing that can handle both hardware and software tasks. The algorithms proposed reuse hardware tasks to reduce reconfiguration overhead, migrate tasks between software/hardware, and give priority to hardware tasks. Results obtained indicate that adding a software processor element not only adds flexibility, but also increases system performance. Two on-line schedulers were designed and implemented. RCSched-I is a simple based implementation that nominates the first available free Partial Reconfigurable Region (PRR) for new tasks. RCSched-II on the other hand nominates any free PRR. Both schedulers check the nominated PRR(s) against the ready task for a match, then decide if there is a need for reconfiguration or not. RCSched-II reconfigures the least recently configured PRR, which increases hardware tasks reuse and decreases total processing time.

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Section: Related Workmentioning

confidence: 99%

Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems

Al-Wattar

Areibi

Saffih

2012

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

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“…Our solution's runtime is typical of heuristics, i.e., tens of milliseconds (see Section V), whereas meta-heuristics normally require seconds or minutes to produce a solution [5]. In list scheduling [6]- [8], individual tasks are sorted in a priority list and assigned, in sequence, to the earliest available unit that fits their resource request. Priorities can be assigned statically or dynamically based on di erent characteristics, e.g., execution time, resource occupancy.…”

Section: Rmentioning

confidence: 99%

Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures

Bertolino

Pacalet

Apvrille

et al. 2020

2020 23rd Euromicro Conference on Digital System Design (DSD)

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In modern cloud data centers, reconfigurable devices can be directly connected to a data center's network. This configuration enables FPGAs to be rented for acceleration of dataintensive workloads. In this context, novel scheduling solutions are needed to maximize the utilization (profitability) of FPGAs, e.g., reduce latency and resource fragmentation. Algorithms that schedule groups of tasks (clusters, packs), rather than individual tasks (list scheduling), well match the functioning of FPGAs. Here, groups of tasks that execute together are interposed by hardware reconfigurations. In this paper, we propose a heuristic based on a novel method for grouping tasks. These are gathered around a high-latency task that hides the latency of remaining tasks within the same group. We evaluated our solution on a benchmark of almost 30000 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 71.3% of the cases. It produces solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 88.1% of the cases.

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“…Some of the commonly used methods for scheduling hardware and software tasks are briefly described as follows. Loo and Wells [2005] used list scheduling with random priority, ASAP priority, and ALAP priority in their reconfigurable system design model. Mei et al [2000] applied list scheduling with dynamic priority that combines dynamic ASAP and ALAP scheduling criteria.…”

Section: Previous Workmentioning

confidence: 99%

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

Hsiung

Huang

Shen

et al. 2010

ACM Trans. Reconfigurable Technol. Syst.

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With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively. -C. 2010. Scheduling and placement of hardware/software real-time relocatable tasks in dynamically partially reconfigurable systems.

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Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment

Cited by 22 publications

References 27 publications

Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems

Efficient On-line Hardware/Software Task Scheduling for Dynamic Run-time Reconfigurable Systems

Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures

Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems

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