Technical Understanding of Resin-Coated-Copper (RCC) Lamination Processes for Realization of Reliable Chip Embedding Technologies

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

“…These packages were processed in a large panel format and they were separated using a laser or a standard (wafer) saw. More details regarding the QFN chip embedding, assembly and processing steps can be found in references [12]. For the embedded QFN packages, we investigated these packaged chips after two of the most potentially decisive processing steps marked by black square boxes in Fig.…”

“…During the lamination process, the die bonded Si chip on the core substrate is covered from the top side with an RCC layer in a pressurised chamber. A pressure > 12 bar is required to ensure sufficient flow of the RCC dielectric in order to prevent the formation of voids around the chips [4]. It is likely that stress is generated during this process as a consequence of the use of high pressure.…”

“…The fabrication process of a complete packaged IC is a tricky one, as it involves the use of different materials of distinct coefficients of thermal expansion (CTEs), e.g. die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11].…”

“…Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11]. Other factors such as the bonding of wires to the die itself [3], thinning of the wafer/die below 100 µm and embedding/lamination processes can also lead to stress and induced warpage/material deformation [12][13]. The process-induced stresses can even be large enough to induce cracking or interfacial delamination in the package, which by potentially degrading the performance and reliability of the packaged chip, could ultimately lead to device failure.…”

“…Scanning acoustic microscopy (SAM) [14,15], scanning electron microscopy (SEM) [15] and X-ray radiography [12,13] are the most commonly used techniques for characterising packaged chip integrity, such as die cracking and delamination inside packaged chips, but none of these techniques is capable of quantitatively measuring the magnitudes of stresses or lattice misorientations inside packaged chips [16]. A recently developed synchrotron X-ray technique based on 3-dimensional X-ray diffraction imaging combined with 3-dimensional surface modelling (3DSM) has, for the first time, enabled the non-destructive imaging and measurement of strain and internal damage in packaged Si chips [17].…”