Test and Characterization of a Variable-Capacity Multilevel DRAM

Koob, J.C.; Ung, S.A.; Rao, A.S.M.; Leder, D.A.; Joly, C.; Breen, Kristopher; Brandon, T.L.; Hume, M.; Cockburn, B.F.; Elliott, D.G.

doi:10.1109/vts.2005.82

Cited by 4 publications

(3 citation statements)

References 7 publications

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“…An approach that has been used successfully in multilevel DRAM is to create the copies of the cell signal by partitioning each bitline into two or more equal-capacitance subbitines [6,7]. In the case of ternary FeRAM, the cell charge could first be dumped onto two connected subbitlines, then the two copies of the cell signal could be created by opening a transistor switch.…”

Section: Fig 6 Write Operations In Ternary Ferammentioning

confidence: 99%

“…Only eight of those states are required to encode three bits, implying an average storage density of 1.5 bits per cell. (Such an encoding has been used previously in experimental multilevel DRAMs at the University of Alberta [6,7].) The translation to and from external binary information to ordered pairs of ternary values can be readily accomplished using combinational logic in the peripheral circuitry.…”

Section: Introduction *mentioning

confidence: 99%

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An Investigation into Three-Level Ferroelectric Memory

Raiter

Cockburn

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)

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Section: Fig 6 Write Operations In Ternary Ferammentioning

confidence: 99%

Section: Introduction *mentioning

confidence: 99%

An Investigation into Three-Level Ferroelectric Memory

Raiter

Cockburn

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05)

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“…This voltage is then amplified to regain the saved voltage. In the MV DRAM [6,9,10] case, the signal does not only has to get amplified, the levels also has to be differentiated. For this to possible with the same amount of charge pr.…”

Section: Memorymentioning

confidence: 99%

Self-refreshing Multiple Valued Memory

Lomsdalen

Jensen

Berg

2006 IEEE Design and Diagnostics of Electronic Circuits and Systems

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This paper introduces a structure for self-refreshing Multiple Valued Memory. The idea is to use structures having repeating patterns, to represent different saved values. Assuming a clocked repeating finite pattern, each pattern will repeat themselves after a finite number of clock pulses N, having N different phases. The values saved will be represented by both a pattern, and the phase of the pattern. The criterion for being selfrefreshing is being fulfilled by resetting the pattern to a known value at least once every period. Some of these structures are quite possible to implement without a linear relation between the levels saved (radixes) and the number of transistors. This can make it competitive as memory for some certain Multiple Valued Logic applications, being integrated between logic structures on chip.

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Auto-calibration technique for on-chip reference voltage generation in ferroelectric memories

Raiter

Cockburn

Canadian Conference on Electrical and Computer Engineering, 2005.

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Test and Characterization of a Variable-Capacity Multilevel DRAM

Cited by 4 publications

References 7 publications

An Investigation into Three-Level Ferroelectric Memory

An Investigation into Three-Level Ferroelectric Memory

Self-refreshing Multiple Valued Memory

Auto-calibration technique for on-chip reference voltage generation in ferroelectric memories

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