Test challenges in nanometer technologies

Abstract

Scaling transistor feature size allows greater density, higher performance and lower cost. The unrelenting pursuit of device scaling has enabled MOS gate dimensions to be reduced from IO-m in the 1970's to a present day size of 0.1-m. Conventional scaling of gate oxide thickness, source/drain extension, junction depths, and gate lengths have brought about several new technology issues invalidating some earlier methods for testing ICs. To enable testing devices into the 21'' century, new approaches are required in both test and design for testability.In this paper, we will define the problems that arise with device scaling such as Gate Oxide leakage, sub-threshold leakage, power density, electromigration, and soft error problems in qualitative and quantitative terms. The later half of the paper deals with some of the solutions being pursued at Intel.

Investigation into voltage and process variation-aware manufacturing test

“…[142,24,143] and recent research [151,149,150] has reported negative impact on manufacturing test quality. In particular, as it will be shown in this chapter, process variation influences the behaviour of resistive bridging faults (RBF), which is a major defect type in CMOS [64].…”

“…Process variation causes the manufactured chips to deviate from the specification to which they were designed [142,143], including variations in delay and leakage power [24].…”

“…The likelihood of cross-talk and soft errors (transient failures due to influence from outside the IC, for example radiation of charged particles) is elevated in designs that are affected by process variation [142]. To measure process variation, the study in [144] and the study in [145] suggested to include sensors on-chip.…”

Test Set Development for Cache Memory in Modern Microprocessors

“…At the same time, as the dimensions of manufactured devices decrease, new more complex memory faults are observed that require specialized memory tests to ensure their detection [24]. Keeping in mind that the allowed defect per million (DPM) budget for the entire collection of on-chip memory is extremely low, these trends stress the increasing importance of memory testing in microprocessors today and in the future [33].…”

Tests for address decoder delay faults in RAMs due to inter-gate opens

“…The increasing use of copper wiring will shift the predominant failure mode from shorts and bridges to opens [2]. Needham [3] reports that opens were the most likely cause of field returns of Intel microprocessors.…”