Test Generation for Combinational Quantum Cellular Automata (QCA) Circuits

Gupta, Pallav; Jha, Niraj K.; Lingappan, Loganathan

doi:10.1109/date.2006.244175

Cited by 11 publications

(9 citation statements)

References 19 publications

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“…The results in their work have shown that this conventional test technique for CMOS designs can also be effective in QCA based designs as well. However, this method requires a much larger number of test patterns to achieve the same fault coverage obtained in both this work and in [12].…”

Section: Introductionmentioning

confidence: 55%

“…Table II shows the number of test vectors generated for each of the considered benchmark circuits when using both fixed polarized cells and external inputs to implement the AND and OR gates. The third column shows the results of the SSF test set size generated using SAT in [12] which also assumed fixed polarized cells to implement AND/OR gates. The bolded entries in the table are those which either equal or better the results reported in [12].…”

Section: Resultsmentioning

confidence: 99%

“…The third column shows the results of the SSF test set size generated using SAT in [12] which also assumed fixed polarized cells to implement AND/OR gates. The bolded entries in the table are those which either equal or better the results reported in [12]. While the test set size is considerably smaller for circuits implementing the AND/OR gates using fixed polarized cells, the computational time for the latter method was generally shorter in spite of the larger fault list.…”

Section: Resultsmentioning

confidence: 99%

“…6 that when a path is sensitized, every node along that path is also being sensitized. Thus, for a combinational majority circuit, C, any test set, V , that detects all SSFs on the primary inputs and fanout branches detects all SSFs in C [12]. This particular property is useful for fault collapsing of majority circuits.…”

Section: B Fault Collapsingmentioning

confidence: 97%

“…Most notably, Gupta et al have developed a comprehensive test generation methodology using Boolean satisfiability (SAT) to cover both SSFs and bridging faults in QCA circuits and have tested their automatic test pattern generator (ATPG) on a set of MCNC benchmark circuits [12]. Tahoori et al have investigated test set generation for fanout-free AND/OR circuits in QCA and have suggested test-friendly design architectures that help minimize the number of test vectors required for those majority gate based designs [13]- [15].…”

Section: Introductionmentioning

confidence: 99%

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Testing of combinational majority and minority logic networks

Karim¹,

Walus²,

Ivanov³

2008

2008 IEEE 14th International Mixed-Signals, Sensors, and Systems Test Workshop

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In this paper, we present an extension to the existing PODEM algorithm to include the ability to generate test patterns for majority and minority networks, specifically targeting quantum-dot cellular automata (QCA), but that is directly applicable to other emergent nanotechnologies such as single electron tunneling (SET) and tunneling phase logic (TPL). A dynamic probability-based controllability technique was developed and used as a guide to make more intelligent decisions on which lines to justify during the automatic test pattern generation (ATPG) process. Lastly, a genetic algorithm was used to fill-in the unspecified values in the test patterns produced by the ATPG in order to achieve compaction on the final test set size. The modified PODEM algorithm was tested on a set of MCNC benchmark circuits when using both fixed polarized cells and external inputs to implement the AND and OR gates. Test set sizes were much smaller when implementing the AND/OR gates using fixed polarized cells, however, the computational times for the latter method were generally shorter.

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Section: Introductionmentioning

confidence: 55%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: B Fault Collapsingmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Testing of combinational majority and minority logic networks

Karim¹,

Walus²,

Ivanov³

2008

2008 IEEE 14th International Mixed-Signals, Sensors, and Systems Test Workshop

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Efficient and reliable fault analysis methodology for nanomagnetic circuits

Turvani

Riente

Cairo

et al. 2016

Circuit Theory & Apps

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Summary The increasing issues in scaled Complementary Metal Oxide Semiconductor (CMOS) circuit fabrication favor the flourishing of emerging technologies. Because of their limited sizes, both CMOS and emerging technologies are particularly sensitive to defects that arise during the fabrication process. Their impact is not easy to analyze in order to take the necessary countermeasures, especially in the case of circuits of realistic complexity based on emerging technologies. In this work, we propose a new methodology supported by an efficient and reliable tool for the identification of the impact of faults in complex circuits implemented using the emerging technology we are focusing on in this case: nanomagnetic logic. The methodology is based on three main steps: (i) we performed exhaustive physical‐level simulations of basic blocks based on a detailed finite‐element tool in order to have a full characterization, to know their properties in presence of defects, and to have a solid reference point for the following steps; (ii) we developed a model (fanomag) for the basic block behavior suitable for simulations in presence of defects of complex circuits, that is, lighter than a physical level one, but accurate enough to capture the most important features to be inherited at circuit level; (iii) starting from a physical design of complex circuits that we perform using a specific design tool we developed, that is, ToPoliNano, we simulated using fanomag, now embedded in our ToPoliNano tool, the behavior of circuits in presence of multiple sets of fabrication defects using a Monte Carlo approach now included in ToPoliNano as a new feature. In this paper, a specific type of defect is considered as a case study. The framework and methodology are conceived to be easily extended to handle other types of defects and problems due to working conditions that a designer and/or a technologist might want to focus on. The major outcome is then a powerful methodology and tool capable to analyze with a good accuracy nanomagnetic logic complex circuits and architectures both in ideal conditions and in presence of defects with remarkable performance in terms of simulation times. Copyright © 2016 John Wiley & Sons, Ltd.

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