Test of data retention faults in CMOS SRAMs using special DFT circuitries

Champac, Victor; Avendano, V.

doi:10.1049/ip-cds:20040431

Cited by 4 publications

(1 citation statement)

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“…T pause or T BC_occupied . T pause , no more e-SRAM tests can be grouped into mg i , and hence we proceed to generate a new memory test group (lines [11][12][13]. Otherwise, we first try to find a compatible e-SRAM test with maximum power consumption that is able to fit in without conflicts (see Fig.…”

Section: Because Of This Fixed Wait Period Whenever An 'A' Type Of Mmentioning

confidence: 99%

Test scheduling for built-in self-tested embedded SRAMs with data retention faults

Wang

Ivanov

et al. 2007

IET Comput. Digit. Tech.

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The test scheduling problem for built-in self-tested embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered is addressed here. We proposed a 'retention-aware' test power model by taking advantage of the fact that there is near-zero test power during the pause time for testing DRFs. The proposed test scheduling algorithm then utilises this new test power model to minimise the total testing time of e-SRAMs while not violating given power constraints, by scheduling some e-SRAM tests during the pause time of DRF tests. Without losing generality, we consider both cases where the pause time for DRFs is fixed and cases where it can be varied. Experimental results show that the proposed 'retention-aware' test power model and the corresponding test scheduling algorithm can reduce the testing time of e-SRAMs significantly with negligible computational time.

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Section: Because Of This Fixed Wait Period Whenever An 'A' Type Of Mmentioning

confidence: 99%