Test of Reconfigurable Modules in Scan Networks

Cantoro, Riccardo; Zadegan, Farrokh Ghani; Palena, Marco; Pasini, Paolo; Larsson, Erik; Reorda, M. Sonza

doi:10.1109/tc.2018.2834915

Cited by 13 publications

(6 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed methodology is based on previous work focused on generating efficient patterns to perform end-ofmanufacturing test for RSNs [3]. The detection mechanism introduced first in [4] and then adopted in several works [5], [6] has been modified to reduce significant overhead and has been made more suitable for addressing the presented problem.…”

Section: Methodsmentioning

confidence: 99%

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Damljanovic

Jutman²,

Squillero

et al. 2019

2019 IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

The increasing number of embedded instruments used to perform test, monitoring, calibration and debug within a semiconductor device has called for a brand new standardthe IEEE 1687. Such a standard resorts to a reconfigurable scan network to provide efficient and flexible access to instruments and to handle complex structures. As it has to deliver reliable service, many approaches, both formal and simulation-based, have been proposed in the literature to perform test, diagnosis and verification of such networks. This paper focuses on the problem of post-silicon validation of a network, a problem that has not been adequately addressed, yet. We analyze the mismatches between the specification and its silicon implementation, and we propose a methodology to detect a subset of them by applying functional patterns and observing the length of the active scan path. Experimental results on ITC2016 benchmarks demonstrate that the proposed approach is broadly applicable, and able to generate very effective sequences. We also classify mismatches that cannot be targeted relying exclusively on the active scan path length information.

show abstract

Section: Methodsmentioning

confidence: 99%

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Damljanovic

Jutman²,

Squillero

et al. 2019

2019 IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

show abstract

“…Several works have addressed testing and localization (diagnostic) for regular scan chains [10]- [12] and for IEEE Std. 1687 networks [13]. Kundu [10] presented an early work on testing and diagnosing faults in scan chains.…”

Section: Related Workmentioning

confidence: 99%

Graceful Degradation of Reconfigurable Scan Networks

Larsson

Xiang

Murali

2021

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track and updating description languages for each individual IC, we propose an on-chip hardware block that makes adjustments according to the fault status of a particular IC. We show how this block enables test for faulty scan chains, localization of faulty scan chains, and repair by excluding faulty scan chains. We made implementations and experiments to evaluate the overhead in terms of transported data and area.

show abstract

“…Cantoro et al proposed techniques to test the IEEE Std. 1687 network [10]. Jutman et al proposed the first work with IEEE Std.…”

Section: Related Workmentioning

confidence: 99%

IEEE Std. P1687.1: Translator and Protocol

Larsson

Murali

Kumisbek

2019

2019 IEEE International Test Conference (ITC)

Self Cite

View full text Add to dashboard Cite

The IEEE Std. P1687.1 working group is currently exploring alternatives to IEEE Std. 1149.1 test access port (TAP) as the interface between the boundary of integrated circuits (ICs) and IEEE Std. 1687 networks. In this paper, we investigate the use of universal asynchronous receiver-transmitter (UART) to access IEEE Std. 1687 networks. We have developed a protocol to describe the information transported over UART and a hardware component to translate (retarget) information between UART and IEEE Std. 1687. The objective is to minimize the amount of information transported over UART and the area of the hardware component while maintaining the flexibility to access an arbitrary combination of instrument in the IEEE Std. 1687 network. We have developed software for the protocol translation, implemented the hardware component and IEEE Std. 1687 networks of different sizes in an field-programmable gate array (FPGA). For comparison, we developed a number of alternatives, all implemented on FPGA. The experimental results show that proposed scheme gives low overhead in terms of transported information (data) and low area of the hardware component.

show abstract

Test of Reconfigurable Modules in Scan Networks

Cited by 13 publications

References 19 publications

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

Graceful Degradation of Reconfigurable Scan Networks

IEEE Std. P1687.1: Translator and Protocol

Contact Info

Product

Resources

About