Testing flash memories

Mohammad, M.G.; Saluja, Kewal K.; Yap, Alex

doi:10.1109/icvd.2000.812641

Cited by 25 publications

(11 citation statements)

References 5 publications

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“…These models categorize the faults according to the number of coupling cells associated with each fault type. CFDiSt Class 1 model encompasses both Single and Exclusive fault models that were developed in [4]. In the following discussion, we will use the convention ( j / i ) to denote operation "j" on the coupling cell that sensitizes fault "i" in the coupled cell.…”

Section: Disturbances Vs Coupling Faultsmentioning

confidence: 99%

“…We describe the coupling behavior of the faults under the three different fault models developed in [4]. Modeling disturbances as coupling faults justify the appropriateness of using RAM test algorithm to test flash memories.…”

Section: Introductionmentioning

confidence: 99%

“…Cell reliability issues of the different cell structures and memory organization are discussed in [ 2 ] . Recently, there have been some efforts in the modeling and test of flash memory disturbances [4]. In [4] we described three disturbances/faults that are specific to flash memories using floating gate transistor as the core memory element.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, there have been some efforts in the modeling and test of flash memory disturbances [4]. In [4] we described three disturbances/faults that are specific to flash memories using floating gate transistor as the core memory element. These faults are DC-Programming (DC-P), DC-Erasure (DC-E), and Drain Disturbance (DD).…”

Section: Introductionmentioning

confidence: 99%

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Flash memory disturbances: modeling and test

Mohammad

Saluja

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

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Non Volatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this papel; we develop a coupling fault model that appropriately models disturbances in Flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive Pseudo-algorithms that can be used in testing flash memories. In addition we present an eficient test that detects these disturbances under diflerent fault models developed in this papel:

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Section: Disturbances Vs Coupling Faultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Flash memory disturbances: modeling and test

Mohammad

Saluja

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

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“…ID Code Read [9], reading the manufacturer ID and device ID, is used as a DC interconnect test. March used as an AC function test is a popular algorithm [7][8] [10] as follows: erase, program and read sector by sector. Checkerboard also used as data retention is as follows: erase, program checkerboard pattern and read.…”

Section: Usage Of the Bistmentioning

confidence: 99%

External memory bist for system-in-package

Yamasaki

Suzuki

Kobayashi

et al.

IEEE International Conference on Test, 2005.

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This paper presents the design and implementation of an External Memory Built-In Self-Test (BIST) in Systemon-Chip (SoC) designed for System-in-Package (SiP). We implemented the BIST handshaking with the internal bus in the microcontroller core for the purpose of enabling the BIST to access the CPU address space. This implementation allows to reduce the area overhead of the BIST and vary the test conditions flexibly according to each phase of debugging, reliability evaluation and massproduction test. For testing SDRAM and Flash, we also designed a microcode based algorithmic pattern generator with enough loop-counters, an infinite looping function and a multiple command sequence generator. This BIST method was applied to consumer products with the IEEE 1149.1 JTAG TAP controller, and enabled multitest for mass-production on a burn-in tester.

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A destructive evolutionary algorithm process

Sullivan

Ryan

2009

Soft Comput

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This paper describes the application of evolutionary search to the problem of flash memory wear-out. Flash memory differs from standard RAM in that it can wear out due to the manner in which it is programmed. The operating parameters, such as voltage levels, of flash memory are notoriously difficult to determine, as the optimal values vary from batch to batch. The current method in use is an expensive and time-consuming manual process of destructive testing. Understandably, this process is normally undertaken only at design time and testing on individual batches is normally not feasible. The results are sub-optimum solutions which do not minimise wear-out over the lifetime of the device. This is an enormously important issue in manufacturing, as most Flash Memory devices requiring reliability (e.g. solid state device disk drives) often have 100% or more redundancy to compensate for the wear-out rates. We establish the viability of a hardware platform that utilises an Evolutionary Algorithm to perform destructive experimentation on hard silicon in order to discover optimal or, at least favourable, operating parameter settings automatically in a manufacturing environment. Here, we describe this hardware and reveal results demonstrating an average life extension of between 250 and 350% over the factory set conditions with a maximum life extension exhibited of 700% all for cells within the same device over the factory settings. Furthermore, since the process is automated, it is possible to leverage the spread between process batches to further enhance device specifications, facilitating the near no-cost life extension of a split-gate flash memory device.

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Testing flash memories

Cited by 25 publications

References 5 publications

Flash memory disturbances: modeling and test

Flash memory disturbances: modeling and test

External memory bist for system-in-package

A destructive evolutionary algorithm process

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