The Analysis of System-Level Timing Failures Due to Interconnect Reliability Degradation

Guo, Jin; Papanikolaou, Apostolos; Stucchi, M.; Croes, Kristof; Tőkei, Zs.; Catthoor, Francky

doi:10.1109/tdmr.2008.2006986

Cited by 5 publications

(3 citation statements)

References 30 publications

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“…To determine the time to breakdown, the leakage current under a fixed electrostatic potential stress is measured as a function of time. 19 Similarly, the total charge-to-breakdown calculated from the leakage current measurements will be used to examine the role of electron fluence in TDDB failure.…”

mentioning

confidence: 99%

“…24 By fitting the measurement results at elevated stress levels to a physical model, it is possible to estimate the reliability of the dielectric under typical (low-field) operating conditions. 19 Several competing field breakdown-acceleration models have been proposed to describe the TDDB behavior of low-k dielectrics, with the most prominent showing the log of the time to breakdown (t BD ) proportional either to E (thermochemical a)…”

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confidence: 99%

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Time-dependent dielectric breakdown of plasma-exposed porous organosilicate glass

Nichols

Sinha

Wiltbank

et al. 2012

Applied Physics Letters

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confidence: 99%

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confidence: 99%

Time-dependent dielectric breakdown of plasma-exposed porous organosilicate glass

Nichols

Sinha

Wiltbank

et al. 2012

Applied Physics Letters

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“…From the EM studies it is noted that the interconnect reliability in ICs is most important issues as technology node advances in order to ensure its reliability. Recent work [32] showed that chip failures because of power grid issues, where EM already being discovered by chip designers. Analysis of power grid is becoming a required addition to many design flows.…”

Section: Improvement Of Interconnect Reliabilitymentioning

confidence: 99%

A Review of the Study on the Electromigration and Power Electronics

Rahman¹,

Musa²,

Neher³

et al. 2016

JECTC

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Electromigration is a main challenge in the pursuit of power electronics, because physical limit to increase current density in power electronics is electromigration (EM), whereas much higher electrical current and voltage are required for power electronics packaging. So the effect of EM is an important issue in applications where high current densities are used, such as in microelectronics and related structures (e.g., Power ICs). Since the structure size of integrated circuits (ICs) decreases and the practical significance of this effect increases, the result is EM failure. On the other hand, in the next generation power electronics technology electrical current density is expected to exceed 10 7 A/cm 2 which is another challenge. This review work has been carried out to identify the mechanism of EM damage in power electronics (e.g., pure metallization and solder joints) and also how to control this kind of damage.

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