The determination of zero temperature coefficient point in CMOS transistors

Prijić, Z.; Dimitrijev, Sima; Stojadinović, N.

doi:10.1016/0026-2714(92)90041-i

Cited by 48 publications

(36 citation statements)

References 7 publications

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“…It is desirable to bias the digital and analog circuits meant for wide temperature applications at a point where the V-I characteristics show little or no variation with respect to temperature. This inflection point is typically known as temperature compensation point (TCP) or zero temperature coefficient (ZTC) [6][7][8][9][10]. Previously, Shoucair [11] and Prijic et al [7] have identified the inflection point for a bulk CMOS in both linear and saturation regions for the temperature varying between 25°C and 200°C.…”

Section: Introductionmentioning

confidence: 97%

“…This inflection point is typically known as temperature compensation point (TCP) or zero temperature coefficient (ZTC) [6][7][8][9][10]. Previously, Shoucair [11] and Prijic et al [7] have identified the inflection point for a bulk CMOS in both linear and saturation regions for the temperature varying between 25°C and 200°C. Researchers like Groeseneken et al [9] and Jeon and Burk [1] have experimentally demonstrated the existence of ZTC point for thin and thick film SOI MOSFETs respectively.…”

Section: Introductionmentioning

confidence: 97%

See 1 more Smart Citation

Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

Mohapatra

Pradhan

Sahu

2015

Superlattices and Microstructures

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Section: Introductionmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 97%

Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

Mohapatra

Pradhan

Sahu

2015

Superlattices and Microstructures

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“…In this letter, the ZTC design criterion for a stable integrated circuit under consideration of elevated temperature DT operation means that to drive circuits at an optimal gate voltage with temperature independence is desired. Based on these concepts [5], [6], for the first time, we derived and verified the ZTC point model of a DTMOS transistor for operations at typical room temperatures to military range (25 • C-125 • C). cal solutions for DTMOS, employing an appropriate analytical drain current model is important.…”

Section: Introductionmentioning

confidence: 99%

The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration

Wang

Lin

Chao

2010

IEEE Electron Device Lett.

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For the first time, analytical expressions of zerotemperature-coefficient (ZTC) point modeling of DTMOS transistor are successfully presented in detail. New analytical formulations for the linear and saturation regions of DTMOS transistor operation that make certain the drive current to be temperature independent for the ideal gate voltage are developed. The maximum errors of 0.87% and 2.35% in the linear and saturation regions, respectively, confirm a good agreement between our DTMOS ZTC point model and the experimental data. Compared to conventional MOSFET, the lower V g (ZTC) with higher overdrive current of DTMOS improves the integrated circuit speed and efficiency for the low-power-consumption concept in green CMOS technology.

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“…When the temperature (T) is taking into account, it is necessary to emphasize that TFETs work unlike conventional MOSFETs. The latter present a zero temperature coefficient (ZTC), which is caused, at higher temperatures, by the trade-off between the threshold voltage reduction and the mobility reduction [34]. In TFETs there is no ZTC, as the drain current conduction mechanism (BTBT) increase at higher temperatures due to the bandgap narrowing, resulting in an increase of I ON and not degrading due to mobility degradation observed in MOSFET.…”

Section: Introductionmentioning

confidence: 99%

The impact of the temperature on In0.53Ga0.47As nTFETs

Bordallo¹,

Martino²,

Agopian³

et al. 2018

CompoNano

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ABSTRACT. In this paper, a comparative study between the use of spin on glass and gas phase Zn diffusion of the p++ source of InGaAs TFETs was performed. The use of Zn gas phase doping at the source reduces the tunneling length which results in an enhancement of ION, higher transistor efficiency and intrinsic voltage gain at lower voltages. The main parameters of gas-phased-diffused In0.53Ga0.47As nTFETs with gate stacks composed by 3 nm or 2 nm HfO2 on top of 1 nm Al2O3 have been analyzed. The resulting equivalent oxide thickness (EOT) was about 0.8 nm and 1.0 nm, respectively. The lower EOT improves the electrostatic coupling, resulting in a lower SS (sub 60 mV/dec at room temperature) leading to a higher gm/IDS in weak conduction. TCAD simulations have shown that the ambipolar effect is significant for higher VDS, degrading SS and consequently gm/IDS in the weak conduction regime, also shifting the gm/IDS peak to higher VGS direction due to the increase of IOFF. The AV peak is strongly degraded by an increase of the temperature due to the increase of the trap-assisted-tunneling (TAT) and Shockley-Read-Hall (SRH) generation mechanisms. For higher VGS the AV is lower, and at the same time less sensitive to temperature variations, which is a favorable regime for temperature-dependent analog operation.

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The determination of zero temperature coefficient point in CMOS transistors

Cited by 48 publications

References 7 publications

Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics

The Zero-Temperature-Coefficient Point Modeling of DTMOS in CMOS Integration

The impact of the temperature on In0.53Ga0.47As nTFETs

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