The Devolution of Synchronizers

Beer, Salomon; Ginosar, Ran; Priel, Michael; Dobkin, Rostislav; Kolodny, Avinoam

doi:10.1109/async.2010.22

Cited by 41 publications

(9 citation statements)

References 14 publications

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“…In the past, was believed to improve with technology scaling [4]. However, recent measurements [5] [6] indicate that scaling trends of synchronizers should be re-considered: The need to obtain full characterization may be imperative in technologies beyond 45nm. Because of this, simulation methods that can reliably predict measurements are growing in importance.…”

Section: Introductionmentioning

confidence: 99%

A new 65nm LP metastability measurment test circuit

Beer

Ginosar

2012

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel

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Abstract-Recent synchronizer metastability measurements indicate degradation of MTBF with technology scaling, calling for measurement and calibration circuits in 65nm and beyond. Degradation of parameters can be even worse if the system is operated at extreme supply voltages and temperature conditions. In this work we study the behavior of synchronizers in a broad range of supply voltage and temperature corners. A digital on-chip measurement system is presented that helps to characterize synchronizers in future technologies and a new calibrating system to account for supply voltage and temperature changes is shown. Measurements are compared to simulations for a fabricated 65nm bulk CMOS circuit build.

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Section: Introductionmentioning

confidence: 99%

A new 65nm LP metastability measurment test circuit

Beer

Ginosar

2012

2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel

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“…As the rounding between the constant and logarithmic behaviors is solely determined by the chosen sigmoid equation, the¯tting process reported in all cases. [12][13][14] Similarly, a strong dependence of temperature and voltage on the metastability parameters has been reported. 15 These e®ects, however, are somewhat orthogonal to the line of arguments that we followed in this paper: Changing parameters sets (for the same underlying type of behavior) can be easily accommodated in our model without changing its fundamental structure or the key observations that we reported above.…”

Section: Model¯ttingmentioning

confidence: 99%

A Model for the Metastability Delay of Sequential Elements

Polzer

Steininger

2017

J CIRCUIT SYST COMP

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It is well known that every sequential element may become metastable when provided with marginal inputs, such as input transitions occurring too close or input voltage not reaching a de¯ned HI or LO level. In this case the sequential element requires extra time to decide which digital output level to¯nally present, which is perceived as an output delay. The amount of this delay depends on how close the element's state is to the balance point, at which the delay may, theoretically, become in¯nite. While metastability can be safely avoided within a closed timing domain, it cannot be completely ruled out at timing domain boundaries. Therefore it is important to quantify its e®ect. Traditionally this is done by means of a \mean time between upsets" (MTBU) which gives the expected interval between two metastable upsets. The latter is de¯ned as the event of latching the still undecided output of one sequential element by a subsequent one. However, such a de¯nition only makes sense in a time-safe environment like a synchronous design. In this paper we will extend the scope to so-called value-safe environments, in which a sequential element can safely¯nalize its decision, since the subsequent one waits for completion before capturing its output. Here metastability is not a matter of \failure" but a performance issue, and hence characterization by MTBU is not intuitive. Therefore we will put the focus on the delay aspect and derive a suitable model. This model extends existing approaches by also including the area of very weak metastability and thus providing complete coverage. We will show its validity through comparison with transistor-level simulation results for the most popular sequential elements in di®erent implementations, point out its relation to the traditional MTBU model parameters, namely and T 0 , and show how to use it for calculating the performance penalty in a value-safe environment.

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“…These techniques have been translated into convenient rules of thumb for designers. As digital circuits have become more complex, denser and faster with reduced power consumption, the old rules of thumb are beginning to fail [ 3][ 4], especially when adding process variations and operating-condition sensitivities in today's manufacturing technologies [ 5]. One rule of thumb has stated that the time constant is proportional to the fan-out of four (FO4) propagation delay.…”

Section: Introductionmentioning

confidence: 99%

“…This rule of thumb thus predicts that decreases with feature size and FO4 gate delay. However, a change in this pattern is emerging at process nodes 90nm and below [ 3][ 4] [ 6]. This change is particularly significant when the metastable voltage (typically about ½ ) is in the vicinity of the transistor threshold voltage, an increasingly common occurrence for low-power circuits employing lower supply voltage and high threshold transistors.…”

Section: Introductionmentioning

confidence: 99%

An Extended Metastability Simulation Method for Synchronizer Characterization

Beer

Ginosar

2013

Lecture Notes in Computer Science

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Abstract. Synchronizers play a key role in multi-clock domain systems on chip. Designing reliable synchronizers requires estimating and evaluating synchronizer parameters (resolution time constant) and (metastability window). Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This paper shows that those rules of thumb and some common simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose an extended simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state-of-the-art simulation methods and with measurements of a 65nm LP CMOS test-chip.

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The Devolution of Synchronizers

Cited by 41 publications

References 14 publications

A new 65nm LP metastability measurment test circuit

A new 65nm LP metastability measurment test circuit

A Model for the Metastability Delay of Sequential Elements

An Extended Metastability Simulation Method for Synchronizer Characterization

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