The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations

Dawid, H.; Meyr, H.

doi:10.1109/12.485569

Cited by 72 publications

(34 citation statements)

References 26 publications

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“…It introduces some temporary variables corresponding to the CORDIC variables and , that generically defined as (27) which implies that and . The signs of are, therefore, considered as being differentially encoded signs of in the differential CORDIC algorithm [45]. The rotation and vectoring mode D-CORDIC algorithms are outlined in Table III. D-CORDIC algorithm is suitable for efficient pipelined implementation which is utilized by Ercegovac and Lang [34] using on-line arithmetic based on redundant number system.…”

Section: F Differential Cordic Algorithmmentioning

confidence: 99%

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher

Valls

Juang

et al. 2009

IEEE Trans. Circuits Syst. I

456

198

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Section: F Differential Cordic Algorithmmentioning

confidence: 99%

50 Years of CORDIC: Algorithms, Architectures, and Applications

Meher

Valls

Juang

et al. 2009

IEEE Trans. Circuits Syst. I

456

198

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“…Similarly, all σ i values are computed recursively. Later this technique is implemented with SD arithmetic and proposed as Differential CORDIC (DCORDIC) algorithm [56]. Since the sign calculation of steering variable ( z i ) during absolute value computation takes long time, most significant digit first absolute value technique is employed.…”

Section: Dcordicmentioning

confidence: 99%

“…The implementation of redundant CORDIC with constant scale factor using signed arithmetic results in an increase in the chip area [51][52][53] and latency [51] by at least 50% compared to redundant radix-2 CORDIC [42]. Low latency CORDIC algorithm [55] and differential CORDIC algorithm [56,57] with constant scale factor using CS arithmetic have been proposed to reduce this overhead, the details of which are discussed below. [55].…”

Section: Constant Scale Factor Redundant Cordic Using Csmentioning

confidence: 99%

“…For the iterations i > (n + 1)/2, no correcting factor is required as the scale factor becomes unity. [56]. In the sign estimation methods [51][52][53], half of the computational effort in the x/ y/z data paths of rotational CORDIC is required to allow for the correction of possible errors, as the sign estimation is not entirely perfect.…”

Section: Low Latency Redundant Cordicmentioning

confidence: 99%

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CORDIC Architectures: A Survey

Boppana

Dhar

2010

VLSI Design

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In the last decade, CORDIC algorithm has drawn wide attention from academia and industry for various applications such as DSP, biomedical signal processing, software defined radio, neural networks, and MIMO systems to mention just a few. It is an iterative algorithm, requiring simple shift and addition operations, for hardware realization of basic elementary functions. Since CORDIC is used as a building block in various single chip solutions, the critical aspects to be considered are high speed, low power, and low area, for achieving reasonable overall performance. In this paper, we first classify the CORDIC algorithm based on the number system and discuss its importance in the implementation of CORDIC algorithm. Then, we present systematic and comprehensive taxonomy of rotational CORDIC algorithms, which are subsequently discussed in depth. Special attention has been devoted to the higher radix and flat techniques proposed in the literature for reducing the latency. Finally, detailed comparison of various algorithms is presented, which can provide a first-order information to designers looking for either further improvement of performance or selection of rotational CORDIC for a specific application.

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“…To make the comparison uniform, the scaling circuitry is not considered here, since it is not reported in [4] and [5]. It can be seen clearly that the hardware requirement of the proposed one is less than the others.…”

Section: A Areamentioning

confidence: 99%

A 16-bit CORDIC rotator for high-speed wireless LAN

Maharatna

Troya²,

Banerjee³

et al.

2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE Cat. No.04TH8754)

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-In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm 2 and it dissipates 7 mW power at 20 MHz frequency.

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The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations

Cited by 72 publications

References 26 publications

50 Years of CORDIC: Algorithms, Architectures, and Applications

50 Years of CORDIC: Algorithms, Architectures, and Applications

CORDIC Architectures: A Survey

A 16-bit CORDIC rotator for high-speed wireless LAN

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