The DSP bottleneck

Baines, R.

doi:10.1109/35.392999

Cited by 78 publications

(19 citation statements)

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“…If the following assumptions are made: 1) the additive term should be no more than .5 LSB, then 2) a value for [5], and 3) [see Fig. 4(a)], then the final expression for is obtained…”

Section: Appendix Imentioning

confidence: 99%

“…One of the keys to the success of these systems has been the advance in analog-to-digital converters (ADC's) which convert the continuous-time signals to discrete-time, binary-coded form. As an example, in the telecommunications arena, advances in software radio development [1]- [3] have provided impetus for ADC performance improvements, especially for sampling rates of approximately 100 million samples per second (Ms/s). More generally, the large number of signal types to be digitized has led to a diverse selection of data converters in terms of architectures, resolution, and sampling rates.…”

Section: Introductionmentioning

confidence: 99%

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Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,837

959

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Abstract-Analog-to-digital converters (ADC's) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADC's, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Ms/s), resolution appears to be limited by thermal noise. At sampling rates ranging from 2 Ms/s to 4 giga samples per second (Gs/s), resolution falls off by 1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The recent trend toward single-chip ADC's brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only 1.5 bits for any given sampling frequency over the last six-eight years.Index Terms-Analog-to-digital converters, aperture jitter, comparator ambiguity, input-referred noise, signal-to-noise ratio, spurious-free dynamic range.

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“…If the following assumptions are made: 1) the additive term should be no more than .5 LSB, then 2) a value for [5], and 3) [see Fig. 4(a)], then the final expression for is obtained…”

Section: Appendix Imentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analog-to-digital converter survey and analysis

Walden

1999

IEEE J. Select. Areas Commun.

1,837

959

View full text Add to dashboard Cite

show abstract

“…(1) The filtering and mixing operations are performed on the side of low-rate, and the speed requirement of the convolution operation becomes lower, which decreases the need for high speed devices and modifies the data transmission bottleneck between DSP and the high speed ADC [4].…”

Section: The Efficient Architecture Of the Wide-band Ddcmentioning

confidence: 99%

An efficient implementation architecture for wide-band digital downconversion

Gao

Xiao

2001

J. of Electron.(China)

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The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.

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“…Therefore, different scenes and functional requirements can be realized through the development of APP. For example, it is anti-tamper while it is also an effective means of collection on sensitive electronic information [8]. It is also very useful in the field of defense.…”

Section: R E T R a C T E Dmentioning

confidence: 99%

A Pocket Signal Detector with Smart Phone for Panel

Zhu¹,

Qin²,

An³

et al. 2017

IJCNS

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The DSP bottleneck

Cited by 78 publications

References 0 publications

Analog-to-digital converter survey and analysis

Analog-to-digital converter survey and analysis

An efficient implementation architecture for wide-band digital downconversion

A Pocket Signal Detector with Smart Phone for Panel

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