The first MAJC microprocessor: a dual CPU system-on-a-chip

Kowalczyk, A.; Adler, V.; Amir, C.; Chiu, F.; Chng, Choon Ping; Lange, W.; Ge, Yuefei; Ghosh, S.; Hoang, Tan; Huang, Baoqing; Kant, S.; Kao, Y.S.; Khieu, Cong; Kumar, S.; Lee, Lan; Liebermensch, A.; Liu, Xin; Malur, N.G.; Martin, Ambrozy; Ngo, Hiep; Oh, Sung-Hun; Orginos, I.; Shih, L.; Sur, Balmiki; Tremblay, M.; Tzeng, A.; Vo, D.; Zambere, S.; Zong, Jin

doi:10.1109/4.962280

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…This approach is the one used by modern multithreaded machines such as Niagara [Krewell 2003], Cyclops [Caşcaval et al 2002], and MAJC [Kowalczyk et al 2001]. The advantage of this second approach is that fewer threads are required, particularly if cache misses are infrequent.…”

Section: Hardware Support For Multithreadingmentioning

confidence: 97%

Real-time rendering systems in 2010

Mark

Fussell

2005

ACM SIGGRAPH 2005 Courses on - SIGGRAPH '05

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We present a case for future real-time rendering systems that support non-physically-correct global illumination techniques by using ray tracing visibility algorithms, by integrating scene management with rendering, and by executing on general-purpose single-chip parallel hardware (CMP's). We explain why this system design is desireable and why it is feasible. We also discuss some of the research questions that must be addressed before such a system can become practical.

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Section: Hardware Support For Multithreadingmentioning

confidence: 97%

Real-time rendering systems in 2010

Mark

Fussell

2005

ACM SIGGRAPH 2005 Courses on - SIGGRAPH '05

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“…[9] (or Bwrite^accesses to [10]) other partitioned register files. The third kind of ICC mechanisms is via some common storage resources, such as shared memory or specific shared registers [11]. Table 1 shows the comparison of ICC mechanisms [6].…”

Section: Clustered Architecturesmentioning

confidence: 99%

“…For a centralized register file for N FU, where each FU can read or write any register directly, the area complexity is N 3 , the access delay is N 3/2 , and the power dissipation is N 3 [4]. Therefore, register files in modern wide-issue microprocessors are usually partitioned to reduce hardware complexity [5][6][7][8][9][10][11][12]. Figure 2 shows a generic clustered architecture, where each FU has direct accesses only to a subset of the register file.…”

Section: Clustered Architecturesmentioning

confidence: 99%

Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications

Lin

Chen

Kuo

et al. 2007

J Sign Process Syst Sign Image

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This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1õ26.0%. The DSP has been fabricated in the UMC 0.13 mm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2 Â 3.15 mm 2 including 160 KB onchip SRAM.

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“…For highperformance designs, clock frequencies are further increased by architectural trends favoring deeper pipelines with fewer gates per pipeline stage. Traditionally, designers target clock skews of about 10% of the clock period [21,27,20,16,18]. Long wire delays and variations in buffer delay make these targets challenging.…”

Section: Introductionmentioning

confidence: 99%