The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design

Radway, Robert M.; Sethi, Khushal; Chen, W.-C.; Kwon, Jung‐Dae; Liu, S.; Wu, T.F.; Beigne, E.; Shulaker, Max M.; Wong, H.-S. Philip; Mitra, Sugata

doi:10.1109/iedm19574.2021.9720647

Cited by 16 publications

(5 citation statements)

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“…The proposed implementation achieves lower latency/sample compared to the software version and the 24-bit fixed precision FPGA algorithm performs very similarly to the full precision software version. [22]- [31]…”

Section: B Datasetmentioning

confidence: 99%

Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

Sethi¹

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper, we present first-ever optimized hardware implementation of a state-of-the-art neuromorphic approach Histogram of Averaged Time Surfaces (HATS) algorithm to event-based object classification in FPGA for asynchronous time-based image sensors (ATIS). Our Implementation achieves latency of 3.3 ms for the N-CARS dataset samples and is capable of processing 2.94 Mevts/s. Speed-up is achieved by using parallelism in the design and multiple Processing Elements can be added. As development platform, Zynq-7000 SoC from Xilinx is used. The tradeoff between Average Absolute Error and Resource Utilization for fixed precision implementation is analyzed and presented. The proposed FPGA implementation is ∼ 32 x power efficient compared to software implementation.

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Section: B Datasetmentioning

confidence: 99%

Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

Sethi¹

2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…While continuing to delve into the physical nature of CNTs, novel application-oriented optimization designs should also be carried out based on the advantages of CNTs themselves. For example, the application of CNT in N3XT and N3XT 3D MOSAIC structures (N3XT: Nano-Engineered Computing Systems Technology; MOSAIC: MOnolithic/Stacked/Assembled IC) [ 115 , 116 ]. The N3XT structure contains energy-efficient field-effect transistors (FETs), high-density nonvolatile memories, fine-grained monolithic 3D integration, efficient heat removal, and computation immersed in memory.…”

Section: Discussion and Perspectivesmentioning

confidence: 99%

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

Chen

Zhou

et al. 2022

Micromachines

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Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications.

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“…Appended to the seamless vdW heterogeneous integration, fusion functions such as neuromorphic computing, logic-in-memory, and in-sense computing have moved from device concepts to small-scale array presentation. To make leaps in computational performance requires a new paradigm of integrated performance 8 , where the integrative collaboration of discrete functions can bring the benefits of massive energy and execution time. Hardware systems with sensing, storing, and processing all in one on 2D semiconductors are expected to disrupt the future architecture of electronic applications.…”

Section: Summary and Perspectivesmentioning

confidence: 99%

“…From the top, systems in complex scenarios such as IoT, edge computing require diverse interactions in specific environments 6 , placing increasing demands on the integrated systems for specialized processing applications 7 . But functionally integrated systems place stringent requirements on the heterogeneous integration of the underlying materials 8 .…”

Section: Introductionmentioning

confidence: 99%

2D semiconductors for specific electronic applications: from device to system

2022

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The shrinking of transistors has hit a wall of material degradation and the specialized electronic applications for complex scenarios have raised challenges in heterostructures integration. Intriguingly, two-dimensional (2D) materials have excellent performance even at monolayer. The rich band structures and the lattice-mismatch-free heterostructures can further develop specific mechanisms to meet the demands of various electronic systems. Here we review the progress of 2D semiconductors to develop specific electronic applications from devices to systems. Focusing on the ultra-thin high-performance nanosheets for transistor channels, we consider channel optimization, contact characteristics, dielectric integration. Then we examined 2D semiconductors for specific electronic functions including computing, memory and sense. Finally, we discuss the specific applications of functionalized arrays aiming at problems that are difficult to solve with bulk materials, like the fusion of memory and computation and the all-in-one system.

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The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC, Illusion Scaleup, Co-Design

Cited by 16 publications

References 0 publications

Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

Optimized Implementation of Neuromorphic HATS Algorithm on FPGA

Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects

2D semiconductors for specific electronic applications: from device to system

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