The influence of VLSI technology evolution on radiation-induced latchup in space systems

Johnston, A.H.

doi:10.1109/23.490897

Cited by 132 publications

(47 citation statements)

References 61 publications

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“…This result was expected, as SEL sensitivity has been shown to decrease in modern deep submicron CMOS processes [9] due to the reduced thickness of the epitaxial layer, the presence of retrograde wells and the use of Shallow Trench Isolation (STI). Moreover, device simulation has pointed out the effectiveness of guardrings in substantially decreasing the SEL susceptibility [lo].…”

Section: A Single Event Latchupmentioning

confidence: 91%

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

Faccio

Kloukinas

Marchioro

et al. 1999

IEEE Trans. Nucl. Sci.

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We have studied Single Event Effects in static and dynamic registers designed in a quarter micron CMOS process. In our design, we systematically used guardrings and enclosed (edgeless) transistor geometry to improve the total dose tolerance. This design technique improved both the SEL and SEU sensitivity of the circuits. Using SPICE simulations, the measured smooth transition of the cross-section curve between LET threshold and saturation has been traced to the presence of four different upset modes, each corresponding to a different critical charge and sensitive area. A new architecture to protect the content of storage cells has been developed, and a threshold LET around 89 MeVcm'mg.' has been measured for this cell at a power supply voltage of 2 V.

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Section: A Single Event Latchupmentioning

confidence: 91%

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

Faccio

Kloukinas

Marchioro

et al. 1999

IEEE Trans. Nucl. Sci.

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“…A single latch-up can result in a large current and destruction of the IC or melting of wire bonds supplying power. SEL sensitivity has been observed to decrease in deep submicron processes for a variety of reasons [3] (reduced thickness of the epitaxial layer, retrograde wells, and Shallow Trench Isolation). In addition, the use of guard rings around NMOS devices helps to prevent latch-up.…”

Section: Radiation Damage In Cmos Devicesmentioning

confidence: 99%

Radiation tolerance of prototype BTeV pixel detector readout chips

Chiodini

Appel

Cardoso

et al. 2002

IEEE Trans. Nucl. Sci.

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Abstract--High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pixel detectors (arrays of silicon diodes bump bonded to arrays of front-end electronic cells) is the state of the art technology able to meet these challenges.We report on irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. Prototype pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 micron CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 87 MRad. In addition, non destructive radiationinduced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been extensively measured.

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“…As the Miller capacitor is a fringe metal capacitor placed above the transistors, it does not lead to an increase of the cell area. Single Event Latch-ups (SELs) are mitigated by reducing parasitic resistances associated to the PNPN parasitic structure of CMOS technology [5].…”

Section: Radiation Hardening-by-design Techniquesmentioning

confidence: 99%

Design of rad-hard SRAM cells: A comparative study

Benigni

Liberali

Stabile

et al. 2010

2010 27th International Conference on Microelectronics Proceedings

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Abstract-This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit performance. Simulation results demonstrate that the three cells are functional in all worst case corners. The sensitivity of each cell to single events has been estimated using a fault injection technique. A silicon prototype employing the first cell has been fabricated and characterized.

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The influence of VLSI technology evolution on radiation-induced latchup in space systems

Cited by 132 publications

References 61 publications

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

Single event effects in static and dynamic registers in a 0.25 /spl mu/m CMOS technology

Radiation tolerance of prototype BTeV pixel detector readout chips

Design of rad-hard SRAM cells: A comparative study

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