The layout synthesizer: an automatic Netlist-to-Layout system

Chen, C.C.; Chow, S. M.

doi:10.1145/74382.74422

Cited by 38 publications

(10 citation statements)

References 12 publications

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“…The widely used one-dimensional (1D) style [Barth 1995;Chen and Chow 1989;Hsieh et al 1991;Maziasz and Hayes 1992;Uehara and VanCleemput 1981] is illustrated in Figure 2(b) for the majority circuit of Figure 2(a). It consists of two parallel diffusion islands, called a P/N row, for the PMOS and NMOS transistors, respectively.…”

Section: Cell Layout Stylesmentioning

confidence: 99%

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Gupta

Hayes

2000

ACM Trans. Des. Autom. Electron. Syst.

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A novel technique, CLIP, is presented for the automatic generation of optimal layouts of CMOS cells in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP) and solves both the width and height minimization problems for 2D cells. Width minimization is formulated in a precise form that combines all factors influencing the 2D cell width-transistor placement, diffusion sharing, and vertical interrow connections-in a common problem space; this space is then searched in a systematic manner by the branch-andbound algorithms used by ILP solvers. For height minimization, cell height is modeled accurately in terms of the horizontal wire routing density, and a minimum-height layout is found from among all layouts of minimum width. For exact width minimization alone, CLIP's run times are in seconds for large circuits with 30 or more transistors. For both height and width optimization, CLIP is practical for circuits with up to 20 transistors. To extend CLIP to larger circuits, hierarchical methods are necessary. Since CLIP is optimum under the modeling assumptions, its layouts are significantly better than those generated by other, heuristic, layout tools.

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Section: Cell Layout Stylesmentioning

confidence: 99%

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Gupta

Hayes

2000

ACM Trans. Des. Autom. Electron. Syst.

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“…A reasonably large number of notable contributions have been made over the last fifteen years to the field of transistor placement [1,2,3,4,5,6,7,8]. Generally, transistor placement methods combine the following operations:…”

Section: Transistor Placementmentioning

confidence: 99%

The future of custom cell generation in physical synthesis

Lefebvre¹,

Marple

Sechen

1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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“…However, conventional cell synthesis algorithms focus on minimizing the diffusion gap for CMOS logic cells with series-parallel structure [1][2][3][4][5][6]. To our knowledge there are no studies on cell synthesis algorithms which can use local interconnect in recent Salicide process technolo- In this paper we propose a cell synthesis method for a Salicide process.…”

Section: Introductionmentioning

confidence: 99%

A cell synthesis method for salicide process

Okada¹,

Yamanouchi²,

Kambe³

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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In this paper, we propose a cell synthesis method for a Salicide process. Our method utilizes the local interconnect between adjacent transistors, which is available in some Salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts. The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits. Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wire length.

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The layout synthesizer: an automatic Netlist-to-Layout system

Cited by 38 publications

References 12 publications

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The future of custom cell generation in physical synthesis

A cell synthesis method for salicide process

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