The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique

Tsai, Hsiu-Min; Hsieh, E. R.; Chung, Steve S.; Tsai, Cheng‐Hung; Huang, Ru; Tsai, C. T.; Liang, C. W.

doi:10.1109/vlsit.2012.6242525

Cited by 15 publications

(8 citation statements)

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“…Advanced poly-Si gate bulk planar and trigate CMOS devices, with SiON insulator, were fabricated [7]. The fin width 30nm or 75nm and with various fin heights, 10nm, 15nm, and 30nm, and gate length= 36nm.…”

Section: Device Preparationmentioning

confidence: 99%

“…For a long time, the study of dopant effect on the RDF induced V th variation has been mostly studied by the simulations [3][4][5]; until more recently, an experimental approach becomes feasible [6][7]. profiling of the dopant can be made through the calculation of the local threshold voltage based on an accurate calculation of the channel barrier potential under a varying source-to-drain bias.…”

Section: Principle Of the Discrete Dopant Profilingmentioning

confidence: 99%

“…So far, the understanding of discrete dopant effect on the RDF induced Vth variation has been almost studied by the simulations [3][4][5]. Not until 2011, the understanding of the RDF became possible by using an experimental discrete dopant profiling technique [6][7].…”

Section: Introductionmentioning

confidence: 99%

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Experimental observation on the random dopant fluctuation of small scale trigate CMOS devices

Chung

2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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The random dopant fluctuation is one of the most important issues for sub-50nm CMOS technologies in terms of the device architecture and manufacturing. This paper will demonstrate the methodology to understand the dopant fluctuation via a purely experimental approach. It will be demonstrated in advanced bulk-trigate devices. The discrete dopant distribution along the channel direction can be determined. Boron clustering effect in nMOSFETs can be reasonably explained which results in a larger Vth variation, in comparison to that of pMOSFETs. Moreover, experiments have been extended to the advanced bulk-trigate CMOS devices. The sidewall roughness effect in trigate has also been studied. This approach provides a direct-observation of the random dopant fluctuation (RDF) and is useful for the gate oxide quality monitoring of future generation trigate devices.

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Section: Device Preparationmentioning

confidence: 99%

Section: Principle Of the Discrete Dopant Profilingmentioning

confidence: 99%

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Experimental observation on the random dopant fluctuation of small scale trigate CMOS devices

Chung

2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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“…The understanding of discrete dopant effect on the RDF induced V th variation has been almost studied by the simulations [3][4][5]. Not until 2011, the understanding of the RDF became possible by using an experimental discrete dopant profiling technique [6][7]. Also, with the increasing need on developing the FinFET technology with an attempt to overcome the scaling issue, lots of efforts have been paid on the development of such technology [8][9].…”

Section: Introductionmentioning

confidence: 99%

(Invited) The Random Dopant Fluctuations of Ultra-Scaled CMOS Devices

Chung

2014

ECS Trans.

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This paper demonstrates the methodology to understand the random dopant fluctuation (RDF) from the electrical measurements. The theoretical basis from an experimental discrete dopant profiling technique has first been introduced to analyze the RDF effect. It was further demonstrated on the advanced strain-silicon devices and advanced trigate devices. The discrete dopant distributions along the channel direction can be achieved, followed by the demonstration of the dopant fluctuation in SiC S/D strained and SiGe S/D strained nMOSFETs and pMOSFETs respectively. The carbon or Ge outdiffusion can be easily detected by this method. Finally, experiments have been extended to the advanced bulk-trigate CMOS devices. The sidewall corner effect in trigate has also been studied. It reveals that the corner effect is very challenging for the manufacturing. This approach provides a simple way to monitor the random dopant fluctuation as well as for the quality monitoring of future generation trigate devices.

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“…According to the literature, oxide traps are considered to be the central physical factor responsible for several effects detrimental to the operating characteristics and reliability of metal-oxide-semiconductor transistors. Figure 1-2 presents the typical reliability and fluctuation problems that occurred in miniaturized devices, such as random telegraph noise (RTN) [28], [29], random trap fluctuation (RTF) [30], bias-temperature instability (BTI), and BTI-induced variability [31][32][33], all of which are associated with complex dynamic capture/emission characteristics within gate-oxide traps. The undesirable changes in transistor characteristics posed by these aging mechanisms are of prime practical interest for precise reliability assessment of realistic circuit usage.…”

Section: Reliability Challenges In Nanoscale Mos Devicesmentioning

confidence: 99%

Oxide-defects driven study on reliability and synaptic response characterization of logic devices

Ju¹

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for their technical conversations and knowledge sharing. In particular, I would also like to thank Dr. Lin Ye for being very supportive in many aspects during my doctoral study. Senior Sing Yew, appreciate your patience in helping to proofread the thesis. Your feedback is particularly helpful! Greatest gratitude to their assistance, I can carry out experimental research so smoothly and thoroughly.I would like to owe a vote of thanks to the well-experienced technicians in NTU Semiconductor Characterization Lab, Mr. Seow Yong Hing, Ms. Seet Lye Ping, and Mr. Ng Yong Chiang, for their technical and maintenance support in the prober stations. I also extend my gratefulness and cherish the friendship from Zhiyi, Xinhua, Yuxi, Brain Jia Xu, Fang Qiang, Yuanbo, and all my friends in NTU for their help and lovely companions.In addition, I would like to extend my gratitude to the thesis advisory committee members -Prof. Kim Tae Hyoung and Prof. Tang Xiaohong, for their constructive reviews, sharp proposals, and timely suggestions which have helped me to be more focused on the project direction and enriched my research insight. I am grateful to the Ministry of Education Singapore and Nanyang Technological University for a 4-year generous co-funding research scholarship.Last but not least, I would like to dedicate this dissertation to my familyparticularly my dearest parents Ju Zhoufeng and Liu Yaling. They have always been by my side whenever I need it. Their everlasting love and unconditional care have been constant supports for me to keep moving forward in my life and, I am forever thankful.

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The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique

Cited by 15 publications

References 1 publication

Experimental observation on the random dopant fluctuation of small scale trigate CMOS devices

Experimental observation on the random dopant fluctuation of small scale trigate CMOS devices

(Invited) The Random Dopant Fluctuations of Ultra-Scaled CMOS Devices

Oxide-defects driven study on reliability and synaptic response characterization of logic devices

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