Thermal Limitations of InP HBTs in 80- and 160-Gb ICs

Harrison, I.; Dahlstrom, M.; Krishnan, S.; Griffith, Z.; Kim, Y.M.; Rodwell, M.J.W.

doi:10.1109/ted.2004.824686

Cited by 37 publications

(9 citation statements)

References 12 publications

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“…12, which gives us k = 1.767 × 10 −3 • C −1 (in excellent agreement with the k = 1.741 × 10 −3 • C −1 found in Section III) and dR TH /dT J = 4.988 W −1 . Now, R TH00 can be calculated using (10) for each of the data points of Fig. 2; disregarding the points at V CE = 1 V and V CE = 1.4 V, where the small values of (P D − P D00 ) lead to large errors when R TH00 is extracted from (10), we get an average R TH00 = 436 • C/W (again, in excellent agreement with the R TH00 = 443 • C/W found in Section III).…”

Section: An Alternative Techniquementioning

confidence: 99%

A new method to extract HBT thermal resistance and its temperature and power dependence

Menozzi

Barrett

Ersland

2005

IEEE Trans. Device Mater. Relib.

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This paper introduces a new technique for the measurement of the thermal resistance of HBTs. The method is very simple, because it requires only standard dc I C -V CE measurements taken at different baseplate temperatures, but it is able to account for the dependence of the thermal resistance on both the baseplate temperature and the dissipated power (under the simplifying assumption that the thermal resistance increases linearly with the dissipated power). We have obtained and shown consistent results extracted from devices with an emitter area ranging from 90 µm 2 (1 finger) to 1080 µm 2 (12 fingers). The thermal-resistance values extracted with a standard and wellknown technique are seen to fall inside the range of our results. We have also applied an alternative method that assumes a linear dependence between thermal resistance and junction temperature, and we have shown that both models lead to similar results, which points to the consistency and robustness of our extraction technique.

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Section: An Alternative Techniquementioning

confidence: 99%

A new method to extract HBT thermal resistance and its temperature and power dependence

Menozzi

Barrett

Ersland

2005

IEEE Trans. Device Mater. Relib.

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“…Thermal effects have been identified as a key issue for advanced HBTs [14]. For our devices, the InGaAs subcollector layer (which serves as both an etch-stop layer and to improve collector ohmic contact) has been identified as the major contributor to temperature rise, due to its poor (5 W/K.m) thermal conductivity.…”

Section: B Structure Optimizationmentioning

confidence: 99%

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

Godin

Nodjiadjim

Riet

et al. 2008

2008 IEEE Compound Semiconductor Integrated Circuits Symposium

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Abstract-We report on the development of a submicron InP DHBT technology, optimized for the fabrication of ≥50-GHzclock mixed-signal ICs. In-depth study of device geometry and structure has allowed to get the needed performances and yield. Special attention has been paid to critical thermal behavior. Various size submicron devices have been modeled using UCSD-HBT equations. These large signal models have allowed the design of 50-GHz clocked 50G Decision and 100G Selector circuits. The high quality of the measured characteristics demonstrates the suitability of this technology for the various applications of interest, like 100 Gbit/s transmission.

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“…Mirror current source is another basic circuit which can also be affected by electro-thermal effects that can result in MMIC performance deviations. As a consequence, accurate HBT electro-thermal characterization and modeling is an important issue for successful high-speed integrated circuit simulation and design and for device reliability investigation [2], [3]. Another key feature justifying the important need for electro-thermal characterization and modeling is that a dense integration of transistors having high current densities is required to design high-speed circuits.…”

Section: Introductionmentioning

confidence: 99%

40 ns pulsed I/V set-up and measurement method applied to InP HBT characterization and electro-thermal modeling

Saleh¹,

Chahine²,

Reveyrand³

et al. 2009

2009 IEEE Radio Frequency Integrated Circuits Symposium

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-This paper presents a novel pulsed I/V measurement methodology applied to HBTs characterization using very narrow 40 ns pulse widths. The measurement procedure consists in applying pulsed collector emitter voltages while driving the transistor base with constant DC currents. The proposed measurement technique is applied here to the characterization and electro-thermal modeling of InGaAs/InP DHBTs from Alcatel Thales III-V Lab. By monitoring pulse widths from 400 ns down to 40 ns, non isothermal, quasi isothermal and isothermal behaviors of transistors are observed respectively. Measurements and simulations are then done to study electro-thermal effects in bipolar current mirrors.

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Thermal Limitations of InP HBTs in 80- and 160-Gb ICs

Cited by 37 publications

References 12 publications

A new method to extract HBT thermal resistance and its temperature and power dependence

A new method to extract HBT thermal resistance and its temperature and power dependence

Submicron InP DHBT Technology for High-Speed High-Swing Mixed-Signal ICs

40 ns pulsed I/V set-up and measurement method applied to InP HBT characterization and electro-thermal modeling

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