Thermo-mechanical reliability of 3-D ICs containing through silicon vias

Abstract

In 3-D interconnect structures, process-induced thermal stresses around through-silicon-vias (TSVs) raise serious reliability issues such as Si cracking and performance degradation of devices. In this study, the thermo-mechanical reliability of 3-D interconnect was investigated using finite element analysis (FEA) combined with analytical methods. FEA simulation demonstrated that the thermal stresses in silicon decrease as a function of distance from an isolated TSV and increase with the TSV diameter. Additional simulation suggested that hybrid TSV structures can significantly reduce the thermal stresses. An analytical stress solution was introduced to deduce the stress distribution around an isolated TSV, which was further developed to deduce the stress interaction in TSV arrays based on linear superposition of the analytical solution. We calculated the crack driving force in TSV lines under a thermal load. The effects of TSV diameter, pitch size, and the line configuration on crack driving force were investigated.

Characterization of thermal stresses and plasticity in through-silicon via structures for three-dimensional integration

“…In addition, the method requires special facility that is not easily accessible. Numerical analyses such as finite element analysis (FEA) are commonly used to calculate the magnitude and distribution of stresses in TSV structures [14][15][16]. This method allows the study of complex structures without special experimental facilities.…”

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

“…Established processes are electrodeposition of copper [7,8,11,13,14,18], CVD of tungsten [2,19], CVD of polysilicon [2,12] and the use of low-resistivity silicon [10]. Especially electrodeposition of copper, being a very well-established semiconductor process, is used by many research groups and implemented in most commercialized devices containing TSVs.…”

“…Polymers, especially low-k types with a lower relative permittivity compared to silicon dioxide, are very attractive for the realization of TSVs with improved electrical characteristics [8]. In addition, polymers can further act as a buffer for thermo-mechanical stresses caused by coefficient of thermal expansion (CTE) mismatches [11,18] as their Young's modulus is approximately two orders of magnitude lower as compared to silicon dioxide or silicon nitride.…”

Thermomechanical Reliability Challenges For 3D Interconnects With Through-Silicon Vias

“…Due to the mismatch in the coefficients of thermal expansion (CTEs) of the via materials and Si, thermal stresses are ubiquitously induced during processing and thermal cycling of TSV structures, which can potentially degrade the performance of stress-sensitive devices around the TSVs [8,9] or drive crack growth in 3-D interconnects [9][10][11][12][13]. Therefore, the success of 3-D integration largely relies on the characteristics of thermo-mechanical stresses developed in the system and its impact on performance and reliability.…”

“…Therefore, the success of 3-D integration largely relies on the characteristics of thermo-mechanical stresses developed in the system and its impact on performance and reliability. Finite element methods have been used to numerically analyze the thermo-mechanical stresses in 3-D integrated structures [9][10][11][12][13], typically complicated by specific material processes and structural designs. To assess the themo-mechanical reliability of TSV structures, the driving forces for both cohesive and interfacial crack growth were calculated [12,13].…”