Three-dimensional thin-film-transistor silicon-oxide-nitride-oxide-silicon memory cell formed on large grain sized polysilicon films using nuclei induced solid phase crystallization

Gu, S.H.; Dunton, S.V.; Walker, Andrew; Nallamothu, S.; Chen, E. H.; Mahajani, M.; Herner, S. B.; Eckert, Victoria; Hu, S.; Konevecki, M.; Petti, C.; Radigan, S.; Raghuram, Usha; Vyvoda, M. A.

doi:10.1116/1.2055327

Cited by 8 publications

(10 citation statements)

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“…Our 10-layer NW 3D electronic structure consists of the highest number of functional device layers that have been vertically stacked and reported with any single-crystalline channel material to date. ,− Recent studies using a similar transfer printing of nanomaterials has produced up to three layers with electrical measurements, a factor of 3 less than in this work. In planar Si technology, it has been difficult to achieve true 3D integrated structures, due in part to materials-related challenges associated with high-temperature processing needed to produce single-crystalline silicon.…”

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confidence: 91%

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

et al. 2007

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We report a general approach for three-dimensional (3D) multifunctional electronics based on the layer-by-layer assembly of nanowire (NW) building blocks. Using germanium/silicon (Ge/Si) core/shell NWs as a representative example, ten vertically stacked layers of multi-NW fieldeffect transistors (FETs) were fabricated. Transport measurements demonstrate that the Ge/Si NW FETs have reproducible high-performance device characteristics within a given device layer, that the FET characteristics are not affected by sequential stacking, and importantly, that uniform performance is achieved in sequential layers 1 through 10 of the 3D structure. Five-layer single-NW FET structures were also prepared by printing Ge/Si NWs from lower density growth substrates, and transport measurements showed similar high-performance characteristics for the FETs in layers 1 and 5. In addition, 3D multifunctional circuitry was demonstrated on plastic substrates with sequential layers of inverter logical gates and floating gate memory elements. Notably, electrical characterization studies show stable writing and erasing of the NW floating gate memory elements and demonstrate signal inversion with larger than unity gain for frequencies up to at least 50 MHz. The ability to assemble reproducibly sequential layers of distinct types of NW-based devices coupled with the breadth of NW building blocks should enable the assembly of increasing complex multilayer and multifunctional 3D electronics in the future.Over the past several years, semiconductor NWs 1,2 and carbon nanotubes 3 have been actively explored as the potential materials for future electronic components. These chemically derived single-crystalline nanostructures present unique advantages over conventional semiconductors, as they enable integration of high-performance device elements onto virtually any substrate 4-6 with scaled on-currents and switching speeds higher than state-of-the-art planar Si structures. 7,8 These unique electrical properties and the intrinsically miniaturized dimensions of NW and carbon nanotube building blocks may facilitate the continuation of Moore's law and the evolutionary quest for ever faster and smaller electronics well into the future. More uniquely, the capability of assembling high-performance NW building blocks with diverse functional properties could enable novel circuit concepts such as 3D integrated electronics, 9 where 3D structure arises from sequential assembly 10-12 of NWs into vertically stacked device layers.Indeed, there has been considerable interest in multilayer electronics, as they offer a more efficient interconnection and processing of digital information. [13][14][15] However, materials-and fabrication-related challenges have presented major obstacles in achieving truly 3D integrated circuits based on the conventional Si CMOS technology, and the need for a new technology remains critical. Here, we report the monolithic integration of individual and parallel arrays of crystalline NWs as multifunctional and multilayer circuits...

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confidence: 91%

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

et al. 2007

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“…CMOS post-processing and 3D device integration (1)(2)(3)(4). We recently demonstrated TFTs with competitive mobility values, good ring oscillator performance and low off-state currents (6).…”

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confidence: 99%

Electrical Properties of Plasma-Deposited Silicon Oxide Clarified by Chemical Modeling

et al. 2009

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Our study is focused on Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide films at low temperatures (< 150 oC) using Inductively Coupled (IC) High-Density (HD) plasma source. We recently fabricated Thin Film Transistors (TFTs) with high-quality ICPECVD gate oxides, which exhibited a competitive performance. For better understanding of the influence of deposition parameters on both the deposition kinetics and oxide quality, we have modeled the Ar-SiH4-N2O plasma system with 173 chemical reactions. We simulated concentrations of 43 reactive species (such as e.g. SiHx radicals and SiHx+ (x=0-3) ions, polysilanes, SiO, SiN, SiH3O, SiH2O, HSiO, etc., as well as atomic hydrogen, nitrogen and oxygen) in plasma. We further used our simulations to qualitatively explain (in terms of concentrations of the reactive species) the influence of SiH4/N2O gas-flow ratio and total gas pressure on film electrical properties and deposition rate.

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“…In the meantime, the size of the memory array increases in comparison to the size of the periphery due to aggressively increased bit capacity (see Figure 1.1). Therefore, memory chip development already now drives towards lower thermal budgets, and aims at 3-D integration [3][4][5][6][7][8][9][10].…”

Section: -D Integration Prolongs Moore's Lawmentioning

confidence: 99%

“…chip-to-wafer, waferto-wafer and full monolithic integration) [3,7,8,[10][11][12][13][14][15][16]. Each approach uses different alignment methods, bonding techniques etc., offering different vertical interconnect densities, and hence a various degree of improvement of ICs.…”

Section: -D Integration Prolongs Moore's Lawmentioning

confidence: 99%

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Electronic devices fabricated at CMOS backend-compatible temperatures

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Three-dimensional thin-film-transistor silicon-oxide-nitride-oxide-silicon memory cell formed on large grain sized polysilicon films using nuclei induced solid phase crystallization

Abstract: Articles you may be interested inFabrication and characterization of metal-oxide-nitride-oxynitride-polysilicon nonvolatile semiconductor memory device with silicon oxynitride ( Si O x N y ) as tunneling layer on glass

Cited by 8 publications

References 12 publications

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

Layer-by-Layer Assembly of Nanowires for Three-Dimensional, Multifunctional Electronics

Electrical Properties of Plasma-Deposited Silicon Oxide Clarified by Chemical Modeling

Electronic devices fabricated at CMOS backend-compatible temperatures

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