Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

(Invited) Downscaling Issues in Polycrystalline Silicon TFTs

“…15b: the dV T /dV ds vs V ds curves computed without including impact ionization tend to flatten with increasing V ds while activation of impact ionization produces a substantial increase of the dV T /dV ds in the high V ds region. It should be pointed out that the reduced V T variation with L at higher V ds , observed in SOI devices [21], is not present in polysilicon TFTs, as can be readily realized from Fig. 14. Indeed, as V ds is increased the V T curves tend to spread out, denoting an increased V T roll-off with L. In order to clarify this point and in analogy to the analysis of SOI devices [21], we extracted from the numerical simulations the maximum hole concentration near the source junction, as an index of the strength of the FBE.…”

“…15a and assuming that DIBL and FBE do not interact (this assumption can be regarded only as a first approximation [22]), one could conclude that DIBL is accounting for most of the V T variation in the present devices. On the other hand, as already pointed out by Tsuchiya et al [21], DIBL and FBE mechanisms, in principle, are expected to interact in a complex way, so that DIBL contribution to V T variation could be influenced by the presence of impact ionization and vice versa. The influence of impact ionization in V T lowering is further evidenced in Fig.…”

“…13b, and the dependence of this quantity from L is also well reproduced. Based on the studies performed on fully depleted (FD) SOI MOSFETs, the V T variation observed in polysilicon TFTs can be attributed to three mechanisms: the first mechanism is the DIBL effect on barrier height for electron injection into the channel from source , 33 (5) 3-22 (2010) junction [21]; the second is related to floating body effects (FBE), which are triggered by impact ionization occurring at the drain end of the channel, and the third is the DIBL effect on the barrier for holes, which accumulate near the source. As already mentioned, the holes generated by impact ionization flow towards the source junction, where pile up and induce a positive bias of the drain junction, further reducing the source junction barrier height.…”

Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review

“…Effects of the three mechanisms on threshold voltage dependence on gate length [31]. Threshold voltage versus channel length of an SOI NMOS device with front gate oxide of 6 nm and a thin-film of 100 nm, and buried oxide of 100 nm and 400 nm [37].…”

Modified analytical model for subthreshold current in short channel MOSFET's

“…These departures, so called short-channel effects, arise as a consequence of two-dimensional potential distribution and high electric fields in the channel region [7]. Short-channel effects degrade the controllability of the gate voltage to drain current, which leads to the degradation of the subthreshold slope and the increase in drain off-or leakage current [5].…”