Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

Ding, Yixiao; Chu, Chris; Mak, Wai-Kei

doi:10.1145/2593069.2593233

Cited by 28 publications

(8 citation statements)

References 11 publications

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“…Two options are potentially available to resolve this violation. One is line end extension [9], the other is rip-up and reroute. We prefer the first option if the extension is allowed.…”

Section: Overall Routing Schemementioning

confidence: 99%

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Ding

Chu

Mak

2015

Proceedings of the 52nd Annual Design Automation Conference

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As the technology nodes scale down to 22nm and beyond, Double Patterning Lithography (DPL) has been considered as a practical solution for manufacturing process. Compared with Litho-Etch-Litho-Etch (LELE), Self-Aligned Double Patterning (SADP) has better overlay tolerance. Two types of SADP process are popularly used for the state-of-the-art lithography patterning: Spacer-Is-Dielectric (SID) and Spacer-Is-Metal (SIM). Meanwhile, Self-Aligned Quadruple Patterning (SAQP), as a natural extension of SADP, is expected to be one of the major solutions for future process requirement after the 16nm/14nm technology node. In order to have better decomposability of layout patterns, we consider SIM type SADP/SAQP during detailed routing stage. The idea of color pre-assignment is adopted and a graph model is proposed which greatly simplifies the problem and reduces design rule violation. Then, the negotiated congestion based scheme is applied for detailed routing based on our proposed graph model. Compared with other state-ofart works, our approach does not produce any side overlay error and no design rule violation is reported. Meanwhile, a better solution in terms of total wirelength, via count, routability, and runtime is achieved.

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“…Two options are potentially available to resolve this violation. One is line end extension [9], the other is rip-up and reroute. We prefer the first option if the extension is allowed.…”

Section: Overall Routing Schemementioning

confidence: 99%

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Ding

Chu

Mak

2015

Proceedings of the 52nd Annual Design Automation Conference

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“…This cut process can be done by using a trim mask or cut mask. As mentioned in [14,15], the cut mask can be optimized by the end-cutting approach. That means instead of removing the whole unwanted wires, we just cut up the connectivity of wires by some fixed size cuts, while logical connectivity of the circuit remains the same.…”

Section: Overview Of End-cutting Processmentioning

confidence: 99%

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design

Gao

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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Unidirectional design has attracted lots of attention with the scaling down of technology nodes. However, due to the limitation of traditional lithography, printing the randomly distributed dense cuts becomes a big challenge for highly scaled unidirectional layout. Recently directed self-assembly (DSA) has emerged as a promising lithography technique candidate for cut manufacturing because of its ability to form small cylinders inside the guiding templates and the actual pattern size can be greatly reduced. In this paper, we perform a comprehensive study on the DSA cut mask optimization problem. We first formulate it as integer linear programming (ILP) to assign cuts to different guiding templates, targeting at minimum conflicts and line-end extensions. As ILP may not be scalable for very large size problem, we further propose a speed-up method to decompose the problem into smaller ones and solve them separately. We then merge and legalize the solutions without much loss of result quality. The proposed approaches can be easily extended to handle more DSA guiding patterns with complicated shapes. Experimental results show that our methods can significantly reduce the total number of unresolvable patterns and the line-end extensions for the targeted layouts.

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“…To obtain a manufacturable layout based on SADP with complementary EBL, most of the previous works focus on minimizing overlay errors and e-beam shots during layout decomposition by using integer linear programming (ILP) based algorithms [2,3,6]. However, no previous work is known for optimizing the cutting structures around the symmetry patterns in analog circuits.…”

Section: Introductionmentioning

confidence: 99%

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography

Tseng

Chang

2015

Proceedings of the 52nd Annual Design Automation Conference

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Self-aligned double patterning (SADP) with complementary e-beam lithography (EBL) is one of the most promising hybrid-lithography techniques for sub-20nm designs. The complementary EBL mitigates the deficiencies of using a single cut mask in SADP. However, the low throughput and negative side effects of EBL might significantly increase the manufacturing costs and damage the symmetry properties in analog circuits. In this paper, we present the first work that considers SADP with EBL during analog placement to simultaneously optimize the area, wirelength, overlay errors, and e-beam shots. We first propose an overlay and cut conflict-aware SADP decomposition algorithm to optimize the overlay errors and e-beam shots in a layout. Then, a dynamic programming based module shifting technique is developed based on a symmetry-feasible slicing tree formulation to further minimize the differences of overlay errors and e-beam shots between symmetry modules during analog placement. To explore and obtain a desired placement, an analog placement flow is also presented. Experimental results show that our flow can effectively and efficiently reduce area, overlay errors, and e-beam shots while satisfying the symmetry constraints for analog placement.

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Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout

Cited by 28 publications

References 11 publications

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography

Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design

Cutting structure-aware analog placement based on self-aligned double patterning with e-beam lithography

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