Towards 100% testable FIR digital filters

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

1999

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Test issues in application-specific digital filter datapaths are investigated. It is found that such designs can contain hundreds of redundant faults, making it difficult to accurately determine fault coverage. Since these redundant faults tend to appear in the same general location as test-resistant faults, the presence of many redundant faults can hide significant untested faults despite high overall test coverage. Classes of redundant faults that arise in digital filter datapaths are described, and we propose a suite of techniques for identifying and eliminating the most common redundancies based on arithmetic optimization. The approach is suitable as a front-end to more accurate fault simulation, or can be used in the design process to eliminate redundant logic. The approach is validated as a tool for developing very high-coverage built-in self-test circuits, showing that 100% fault coverage can be achieved in 24k-gate filters with as little as 1% area overhead. When used as a datapath optimization technique, the average area reduction over 15 designs was 8.9%, compared with moderately optimized designs. As a front-end to fault simulation, the approach yielded a 97.9% average reduction in the number of undetected faults across the 15 designs.

Section: B Sxt-add Transformationmentioning

confidence: 99%

Redundancy and testability in digital filter datapaths

Goodby

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

1999

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“…Ripple adder chain structures were used to implement the fixed width datapath baseline designs, where all addition and subtraction operations are the width of the filter output. Scaling was then applied to remove redundant sign bits, shrinking portions of the datapath and enabling further redundancy elimination using logic optimizations [4,5].…”

Section: Resultsmentioning

confidence: 99%

“…6.9.2], a DSP design technique that is commonly used to adjust multiplier gains so that overflow is avoided. There is a close relationship between scaling and testability: scaling not only identifies redundant sign bits, but when these bits are removed, clears the path for other logic optimizations that remove redundant faults [4,5]. Even after scaling, there may be upper adder bits that are "near-redundant", i.e.…”

Section: Introductionmentioning

confidence: 99%

Pseudorandom-pattern test resistance in high-performance DSP datapaths

Goodby¹,

33rd Design Automation Conference Proceedings, 1996

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“…In [2], a short sequence of functional test patterns is proposed, providing fault coverages in excess of 90%; high functional coverage is proven through analysis and high structural coverage is substantiated through fault simulations. Goodby and Orailoglu in [3] develop built-in self-test techniques capable of 100% fault coverage through RT and gate level optimizations that eliminate redundant and random-pattern resistant faults. In [7], a low-cost, parameterizable BIST solution for digital filters is developed through utilization of arithmetic pattern generators.…”

Section: Previous Work and Motivationmentioning

confidence: 99%

Unifying methodologies for high fault coverage concurrent and off-line test of digital filters

Bayraktaroglu

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No

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A low-cost on-line test scheme for digital filters that additionally provides an off-line BIST solution is proposed. The scheme utilizes an invariant of the digital filter in order to detect on-line possible circuit malfunctions. The on-line checking hardware is shared with off-line BIST. The analysis performed indicates that exact 100% fault secureness is attained when the digital filter is designed according to design criteria that we identify in the paper. Furthermore, fault simulations show near 100% fault coverage for off-line BIST.