Towards a Heterogeneous Fault-Tolerance Architecture based on Arm and RISC-V Processors

Abstract

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixedcriticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling faulttolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a softcore RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

“…The Reunion approach [25] proposes a CRT that preserves the existing memory interface, coherence protocols, and consistency models, and uses a '''fingerprint'' to compress the architecture status to reduce the comparison overhead, while authors in [10] developed an offline scheduler synthesis framework for MC processors executing real-time applications that, even in the presence of transient faults, can drive the system to a safe execution state. In [26] and [27], fault-tolerant multi-core and many-core processors are described and compared, while [28] proposes an FPGA methodology that combines two different cores with different performances.…”

Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V

“…Lock-V provides a fault tolerance architecture deployed into two processor architectures, using redundancy and design diversity at the ISA-level (Arm and RISC-V). Targeting low-and high-end devices, Lock-V improves the methodologies and techniques initially proposed in [18], and, for the best of our knowledge, there are no similar implementations beyond the contributions provided by this work. Table 1 shows fault tolerance systems that are closely related to Lock-V, summarizing them in terms of architecture, lockstep approach, redundancy strategy, and design diversity support.…”

“…(2) using micro-architectural diversity [16]; and (3) deploying instruction set architecture (ISA) diversity [17,18]. The combination of these solutions can endow safety/mixed-critical systems with higher protection levels against SEU, mitigating CMF by using fault tolerance along with design diversity.…”

A Framework for Fault Tolerance in RISC-V

“…Also several other works utilize the Rocket implementation for fault tolerance in software [3] or hardware. This includes classic TMR [4], [5] and extraordinary approaches, e.g., a heterogeneous lockstep system with a Rocket and Arm Cortex-A9 core [6]. Another RISC-V lockstep processor is presented in [7].…”